# US 9,436,599 B2 · Flash storage device and method including separating write data to correspond to plural channels and arranging the data in a set of cache spaces

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- Number: US 9,436,599 B2
- Document ID: US9436599B2
- Status: Granted
- Kind: B2
- Application number: 14/100,575
- Filed: 2013-12-09
- Published: 2014-09-04
- Granted: 2016-09-06
- Earliest claimed: 2013-03-01
- Assignees: Silicon Motion, Inc.
- Applicants: Silicon Motion, Inc.
- Inventors: Chang-Kai Cheng; Kuan-Yu Ke
- Web page: https://patentgrep.com/patent/US9436599B2

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/0873: Mapping of cache memory to specific storage devices or parts thereof
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 2212/2022: Flash memory
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A data storage device with a FLASH memory accessed via multiple channels and a FLASH memory control method are disclosed. The control method includes dividing a plurality of blocks of a FLASH memory into groups to be accessed by a plurality of channels separately, each block comprising a plurality of pages; allocating a random access memory to provide a first set of cache spaces for the different ones of the plurality of channels; separating write data issued from a host to correspond to the plurality of channels; and after data arrangement in the first set of cache spaces for every channel is completed, writing data arranged in the first set of cache spaces for every channel to the FLASH memory via the plurality of channels. The control method further includes allocating the random access memory to provide a second set of cache spaces; and using the second set of cache spaces to perform data arrangement for the write data issued from the host when writing the data arranged in the first set of cache spaces for every channel to the FLASH memory.

## Claims

### Claim 1

A data storage device, comprising:
a FLASH memory, comprising a plurality of blocks each with a plurality of pages, wherein the blocks are further grouped to be accessed by a plurality of channels separately; and
a controller coupled to the FLASH memory, comprising:
a computing unit;
a read only memory, loaded with programs to be executed by the computing unit to build firmware for the data storage device; and
a random access memory, allocated according to the computing unit executing the firmware to provide a first set of cache spaces, wherein different cache spaces within the first set of cache spaces correspond to different ones of the plurality of channels, respectively, and every channel corresponds to one cache space of the first set of cache spaces,
wherein:
the computing unit separates write data issued from a host to correspond to the plurality of channels and, after data arrangement that combines non-refreshed data with write data in the first set of cache spaces for every channel is completed, the computing unit writes data arranged in the first set of cache spaces for every channel to the FLASH memory via the plurality of channels;
the computing unit further allocates the random access memory to provide a second set of cache spaces, and different cache spaces within the second set of cache spaces correspond to the different ones of the plurality of channels, respectively and every channel corresponds to one cache space of the second set of cache spaces; and
when writing the data arranged in the first set of cache spaces for every channel to the FLASH memory, the computing unit uses the second set of cache spaces to perform data arrangement for the write data issued from the host.

### Claim 2 (depends on 1)

The data storage device as claimed in claim 1, wherein a unit size for a write operation for each channel of the FLASH memory is K pages, and K is a number.

### Claim 3 (depends on 2)

The data storage device as claimed in claim 2, wherein the computing unit writes data that has been arranged in one unit size in one cache space of the first set of cache spaces to K pages of K blocks of the FLASH memory via the channel corresponding to the one cache space, each unit size corresponding to one write operation of the FLASH memory.

### Claim 4 (depends on 1)

The data storage device as claimed in claim 1, wherein the computing unit separates the write data issued from the host to correspond to the plurality of channels and temporarily stores the write data into the first or the second set of cache spaces to be combined with non-refreshed data for data arrangement.

### Claim 5

A FLASH memory control method, comprising:
dividing a plurality of blocks of a FLASH memory into groups to be accessed by a plurality of channels separately, each block comprising a plurality of pages;
allocating a random access memory to provide a first set of cache spaces, wherein different cache spaces within the first set of cache spaces correspond to different ones of the plurality of channels, respectively, and every channel corresponds to one cache space of the first set of cache spaces;
separating write data issued from a host to correspond to the plurality of channels;
after data arrangement that combines non-refreshed data with write data in the first set of cache spaces for every channel is completed, writing data arranged in the first set of cache spaces for every channel to the FLASH memory via the plurality of channels; and
allocating the random access memory to provide a second set of cache spaces, wherein different cache spaces within the second set of cache spaces correspond to the different ones of the plurality of channels, respectively, and every channel corresponds to one cache space of the second set of cache spaces,
wherein when data arranged in the first set of cache spaces for every channel is being written to the FLASH memory, data arrangement for the write data issued from the host is performed on the second set of cache spaces.

### Claim 6 (depends on 5)

The FLASH memory control method as claimed in claim 5, wherein a unit size for a write operation for each channel of the FLASH memory is K pages, and K is a number.

### Claim 7 (depends on 6)

The FLASH memory control method as claimed in claim 6, wherein data that has been arranged in one unit size in one cache space of the first set of cache spaces is written into K pages of K blocks of the FLASH memory via the channel corresponding to the one cache space, each unit size corresponding to one write operation of the FLASH memory.

### Claim 8 (depends on 5)

The FLASH memory control method as claimed in claim 5, wherein the write data issued from the host is separated to correspond to the plurality of channels and temporarily stored into the first or the second set of cache spaces to be combined with non-refreshed data for data arrangement.