# US 9,436,549 B2 · Storage module and method for improved error correction by detection of grown bad bit lines > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,549 B2 - Document ID: US9436549B2 - Status: Granted - Kind: B2 - Application number: 14/502,738 - Filed: 2014-09-30 - Published: 2016-02-04 - Granted: 2016-09-06 - Earliest claimed: 2014-07-31 - Assignees: SanDisk Technologies LLC - Applicants: SanDisk Technologies Inc. - Inventors: Daniel E. Tuers; Abjiheet Manohar - Web page: https://patentgrep.com/patent/US9436549B2 ## CPC - G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems} - G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)} - G11C 29/00: Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation - G11C 29/025: {in signal lines} - G11C 29/42: using error correcting codes [ECC] or parity check - G11C 29/4401: {for self repair} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes} - H03M 13/1111: {Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms} - H03M 13/152: {Bose-Chaudhuri-Hocquenghem [BCH] codes} - H03M 13/3723: {using means or methods for the initialisation of the decoder} - H03M 13/451: {using a set of candidate code words, e.g. ordered statistics decoding [OSD]} - H03M 13/6325: {Error control coding in combination with demodulation} - G11C 2029/0403: {during or with feedback to manufacture} - G11C 2029/0409: {Online test} - G11C 2029/0411: {Online error correction} - G11C 2029/1208: {Error catch memory} - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract In one embodiment, a storage module comprises a controller and a memory having a plurality of bit lines. The controller detects an uncorrectable error in a code word read from the memory, determines location(s) of grown bad bit line(s) that contributed to the error in the code word being uncorrectable, and uses the determined location(s) of the grown bad bit line(s) to attempt to correct the error in the code word. ## Claims ### Claim 1 A storage module comprising: a memory having a plurality of bit lines; and a controller in communication with the memory, wherein the storage controller is configured to: detect an uncorrectable error in a code word read from the memory; determine at least one location of at least one grown bad bit line that contributed to the error in the code word being uncorrectable; and use the determined at least one location of the at least one grown bad bit line to attempt to correct the error in the code word. ### Claim 2 (depends on 1) The storage module of claim 1, wherein the controller is configured to determine the at least one location of the at least one grown bad bit line by: reading a plurality of additional code words that share the same bit lines as the code word that has the uncorrectable error; and generating a histogram of error frequency of each of the bit lines. ### Claim 3 (depends on 2) The storage module of claim 2, wherein the controller is further configured to: apply a high-pass filter to the histogram to identify the at least one location of the at least one grown bad bit line. ### Claim 4 (depends on 2) The storage module of claim 2, wherein the histogram also indicates an originally-stored value of a bit that was in error. ### Claim 5 (depends on 1) The storage module of claim 1, wherein the controller implements an ECC engine using low-density parity-check (LDPC) code, and wherein the controller is configured modify a log likelihood ratio (LLR) of the ECC engine for the determined at least one location of the at least one grown bad bit line before attempting to correct the error. ### Claim 6 (depends on 1) The storage module of claim 1, wherein the controller implements an ECC engine using BCH code, and wherein the controller is configured to flip at least one bit in the respective determined at least one location of the at least one grown bad bit line before attempting to correct the error. ### Claim 7 (depends on 1) The storage module of claim 1, wherein the controller is configured to store the at least one location of the at least one grown bad bit line for later use in attempting to correct errors in additional code words later read from the at least one grown bad bit line. ### Claim 8 (depends on 1) The storage module of claim 1, wherein the memory is a three-dimensional memory. ### Claim 9 (depends on 1) The storage module of claim 1, wherein the storage module is embedded in a host. ### Claim 10 (depends on 1) The storage module of claim 1, wherein the storage module is removably connected to a host. ### Claim 11 A method for improved error correction by detection of at least one grown bad bit line, the method comprising: performing the following in a storage module comprising a memory having a plurality of bit lines: detecting an uncorrectable error in a code word read from the memory; determining at least one location of at least one grown bad bit line that contributed to the error in the code word being uncorrectable; and using the determined at least one location of the at least one grown bad bit line to attempt to correct the error in the code word. ### Claim 12 (depends on 11) The method of claim 11, wherein the at least one location of the at least one grown bad bit line are determined by: reading a plurality of additional code words that share the same bit lines as the code word that has the uncorrectable error; and generating a histogram of error frequency of each of the bit lines. ### Claim 13 (depends on 12) The method of claim 12 further comprising: applying a high-pass filter to the histogram to identify the at least one location of the at least one grown bad bit line. ### Claim 14 (depends on 12) The method of claim 12, wherein the histogram also indicates an originally-stored value of a bit that was in error. ### Claim 15 (depends on 11) The method of claim 11, wherein the storage module implements an ECC engine using low-density parity-check (LDPC) code, and wherein the method further comprises modifying a log likelihood ratio (LLR) of the ECC engine for the determined at least one location of the at least one grown bad bit line before attempting to correct the uncorrectable error. ### Claim 16 (depends on 11) The method of claim 11, wherein the storage module implements an ECC engine using BCH code, and wherein the method further comprises flipping at least one bit in the determined at least one location of the at least one grown bad bit line before attempting to correct the uncorrectable error. ### Claim 17 (depends on 11) The method of claim 11, wherein the method further comprises storing the at least one location of the at least one grown bad bit line for later use in attempting to correct errors in additional code words later read from the at least one grown bad bit line. ### Claim 18 (depends on 11) The method of claim 11, wherein the memory is a three-dimensional memory. ### Claim 19 (depends on 11) The method of claim 11, wherein the storage module is embedded in a host. ### Claim 20 (depends on 11) The method of claim 11, wherein the storage module is removably connected to a host.