# US 9,436,545 B2 · Semiconducotr memory device including non-volatile memory cell array

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 9,436,545 B2
- Document ID: US9436545B2
- Status: Granted
- Kind: B2
- Application number: 14/165,820
- Filed: 2014-01-28
- Published: 2014-08-07
- Granted: 2016-09-06
- Earliest claimed: 2013-02-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Chi-Sung Oh; Chul-Sung Park; Sang-Bo Lee; Dong-Hyun Sohn
- Web page: https://patentgrep.com/patent/US9436545B2

## CPC

- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/16: Error detection or correction of the data by redundancy in hardware
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/4401: {for self repair}
- G11C 29/785: {with redundancy programming schemes}
- G11C 11/40: using transistors
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- G11C 2029/1202: {Word line control}
- G11C 2029/1204: {Bit line control}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a dynamic random access memory (DRAM) cell array;
a parity bit generator configured to generate a first set of parity bits having at least one bit based on input data received from outside the semiconductor memory device;
a nonvolatile memory cell array configured to store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data and a second set of parity bits corresponding to the first set of parity bits; and
an error correction circuit configured to generate second data as corrected data based on the first data and the second set of parity bits,
wherein the semiconductor memory device is configured to use the second data to select a spare cell included in the DRAM cell array.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the semiconductor memory device is configured to use the second data as corrected data if the first data is different from the input data.

### Claim 3 (depends on 1)

The device according to claim 1, wherein the semiconductor memory device is configured to use the second data to replace a defective word line of the DRAM cell array with a spare word line.

### Claim 4 (depends on 1)

The device according to claim 1, wherein the semiconductor memory device is configured to use the second data to replace a defective column selecting line of the DRAM cell array with a spare column selecting line.

### Claim 5 (depends on 1)

The device according to claim 1, wherein the DRAM cell array includes a normal memory cell array connected to word lines and column selecting lines, and a spare memory cell array connected to spare word lines and spare column selecting lines.

### Claim 6 (depends on 5)

The device according to claim 5, further comprising:
a column decoder configured to generate column selection signals, and to provide the column selection signals to the column selecting lines; and
a spare column decoder configured to generate spare column selection signals based on the second data, and to provide the spare column selection signals to the spare column selecting lines when a defective cell is included in the normal memory cell array.

### Claim 7 (depends on 1)

The device according to claim 1, wherein the second data is anti-fuse program data.

### Claim 8 (depends on 1)

The device according to claim 1, wherein the semiconductor memory device is a stacked memory device in which a plurality of chips communicating data and control signals through a through-silicon-via (TSV) are stacked.

### Claim 9 (depends on 1)

The device according to claim 1, wherein the nonvolatile memory cell array includes an anti-fuse cell array having a plurality of anti-fuse cells.

### Claim 10 (depends on 1)

The device according to claim 1, wherein a number of bits of the first set of parity bits is smaller than a number of bits of the input data.

### Claim 11

A semiconductor memory device, comprising:
a dynamic random access memory (DRAM) cell array;
a nonvolatile memory cell array configured to store input data and a first set of parity bits having at least one bit, the input data and the first set of parity bits received from outside the semiconductor memory device; and
an error correction circuit configured to generate second data as corrected data based on first data corresponding to the input data, the first data being received from the nonvolatile memory cell array, and a second set of parity bits corresponding to the first set of parity bits, the second set of parity bits being received from the nonvolatile memory cell array,
wherein the semiconductor memory device is configured to use the second data to repair a defective cell included in the DRAM cell array.

### Claim 12 (depends on 11)

The device according to claim 11, wherein the semiconductor memory device is configured to use the second data as corrected data if the first data is different from the input data.

### Claim 13 (depends on 11)

The device according to claim 11, wherein the semiconductor memory device is configured to use the second data to replace a defective word line of the DRAM cell array with a spare word line.

### Claim 14 (depends on 11)

The device according to claim 11, wherein the semiconductor memory device is configured to use the second data to replace a defective column selecting line of the DRAM cell array with a spare column selecting line.

### Claim 15 (depends on 11)

The device according to claim 11, wherein the nonvolatile memory cell array includes an anti-fuse cell array having a plurality of anti-fuse cells.

### Claim 16

A semiconductor memory device comprising:
a memory cell array;
a parity bit generator configured to generate a first set of parity bits having at least one bit based on first data received from outside the semiconductor memory device;
an anti-fuse cell array including a plurality of anti-fuse cells configured to store the first data and the first set of parity bits, and to transfer second data corresponding to the first data, and a second set of parity bits corresponding to the first set of parity bits; and
an error correction circuit configured to generate third data as corrected data based on the second data and the second set of parity bits,
wherein the semiconductor memory device is configured to use the third data to select a spare cell of the memory cell array.

### Claim 17 (depends on 16)

The semiconductor memory device of claim 16, wherein the memory cell array includes a plurality of dynamic random memory (DRAM) cells.

### Claim 18 (depends on 16)

The semiconductor memory device of claim 16, wherein a number of bits of the first set of parity bits is smaller than a number of bits of the first data.

### Claim 19 (depends on 16)

The semiconductor memory device of claim 16, wherein the memory cell array includes a normal memory cell array connected to word lines and column selecting lines, and a spare memory cell array connected to one or more spare word lines and one or more spare column selecting lines, and
wherein the third data is address information used to select at least one of the spare word lines and the spare column selecting lines.

### Claim 20 (depends on 19)

The semiconductor memory device of claim 19, further comprising a row comparator circuit configured to compare an input address to the third data, and a column comparator circuit configured to compare an input address to the third data.