# US 9,436,543 B2 · Electronic device and method for protecting an electronic device against unauthorized use > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,543 B2 - Document ID: US9436543B2 - Status: Granted - Kind: B2 - Application number: 14/422,060 - Filed: 2012-09-13 - Published: 2015-08-13 - Granted: 2016-09-06 - Earliest claimed: 2012-09-13 - Assignees: Freescale Semiconductor, Inc. - Applicants: Ray Marshall; Joseph Circello; Norbert Huemmer - Inventors: Ray Marshall; Joseph Circello; Norbert Huemmer - Web page: https://patentgrep.com/patent/US9436543B2 ## CPC - G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)} - B60R 25/00: Fittings or systems for preventing or indicating unauthorised use or theft of vehicles (locks for vehicles E05B77/00-E05B85/00) - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - G06F 11/0721: {within a central processing unit [CPU]} - G06F 21/70: Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - B60R: VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR ## Abstract An electronic device comprising a clock unit and a processing unit connected to the clock unit is described. The clock unit may deliver an output clock signal for operating the processing unit in accordance with the output clock signal. The clock unit may have: a normal mode in which the output clock signal has a low amount of jitter and a normal clock rate to enable normal use of the electronic device, and a failure analysis mode in which the output clock signal has a high amount of jitter or a reduced clock rate, or a high amount of jitter combined with a reduced clock rate, to impede the normal use. The clock unit may be protected against unauthorized re-activation of the normal mode. A method of protecting an electronic device against unauthorized use is also described. ## Claims ### Claim 1 An electronic device comprising a clock unit and a processing unit connected to said clock unit, said clock unit arranged to generate an output clock signal, said processing unit arranged to be clocked by said output clock signal, said clock unit having: a normal mode in which said output clock signal has a low amount of jitter and a normal clock rate to enable normal use of said electronic device and a failure analysis mode in which said output clock signal has a high amount of jitter or a reduced clock rate, or a high amount of jitter combined with a reduced clock rate, to impede said normal use; wherein said clock unit is protected against unauthorized re-activation of said normal mode, and said output clock signal has a shortest possible high time and a shortest possible low time which are not shorter in said analysis mode than in said normal mode. ### Claim 2 (depends on 1) The electronic device of claim 1, further comprising a disable unit connected to said clock unit and arranged to deactivate said normal mode and activate said analysis mode in response to a disable signal. ### Claim 3 (depends on 2) The electronic device of claim 2, wherein said disable unit is arranged to deactivate said normal mode permanently in response to said disable signal. ### Claim 4 (depends on 3) The electronic device of claim 3, wherein said disable unit comprises a dedicated input unit for receiving said disable signal. ### Claim 5 (depends on 2) The electronic device of claim 2, wherein said disable unit comprises a non-volatile memory element having: a first state for enabling said normal mode and a second state for enabling said analysis mode. ### Claim 6 (depends on 5) The electronic device of claim 5, wherein said memory element is one-time programmable. ### Claim 7 (depends on 5) The electronic device of claim 5, wherein said memory element is lockable by means of an electronic key. ### Claim 8 (depends on 1) The electronic device of claim 1, wherein said clock unit is arranged to generate edges of said output clock signal periodically when in said normal mode and randomly or pseudo-randomly when in said analysis mode. ### Claim 9 (depends on 1) The electronic device of claim 1, wherein said clock unit is arranged in both said normal mode and said analysis mode to generate said output clock signal from an input clock signal having a low amount of jitter. ### Claim 10 (depends on 9) The electronic device of claim 9, wherein said clock unit comprises a pseudo-random clock divider arranged to generate said output clock signal from said input clock signal when said clock unit is in said analysis mode. ### Claim 11 (depends on 9) The electronic device of claim 9, wherein said clock unit is arranged to deliver said input clock signal as said output clock signal when said clock unit is in said normal mode. ### Claim 12 A method of protecting an electronic device against unauthorized use, said method comprising: generating an output clock signal in a clock unit, wherein the clock unit is included in said electronic device; clocking a processing unit by said output clock signal, wherein said processing unit is included in said electronic device; operating said clock unit in a normal mode in which an input clock signal having a normal clock rate and a low amount of jitter is delivered as said output clock signal to enable normal use of said electronic device; activating a failure analysis mode in which said output clock signal has a reduced clock rate or a high amount of jitter, or a high amount of jitter combined with a reduced clock rate, to impede said normal use; and protecting said clock unit against unauthorized re-activation of said normal mode. ### Claim 13 (depends on 12) The method of claim 12, further comprising a failure analysis of said electronic device.