# US 9,436,501 B2 · Thread-based cache content saving for task switching

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- Number: US 9,436,501 B2
- Document ID: US9436501B2
- Status: Granted
- Kind: B2
- Application number: 14/468,567
- Filed: 2014-08-26
- Published: 2016-03-03
- Granted: 2016-09-06
- Earliest claimed: 2014-08-26
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Harold W. Cain, III; David M. Daly; Brian R. Prasky; Vijayalakshmi Srinivasan
- Web page: https://patentgrep.com/patent/US9436501B2

## CPC

- G06F 9/5016: {the resource being the memory}
- G06F 9/461: {Saving or restoring of program or task context}
- G06F 9/4843: {by program, e.g. task dispatcher, supervisor, operating system}
- G06F 12/0842: for multiprocessing or multitasking
- G06F 12/0862: with prefetch
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/123: with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
- G06F 2212/1024: Latency reduction
- G06F 2212/251: Local memory within processor subsystem
- G06F 2212/452: Instruction code
- G06F 2212/602: Details relating to cache prefetching
- G06F 2212/6022: Using a prefetch buffer or dedicated prefetch cache
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments relate to thread-based cache content savings for task switching in a computer processor. An aspect includes determining a cache entry in a cache of the computer processor that is owned by the first thread, wherein the determination is made based on a hardware thread identifier (ID) of the first thread matching a hardware thread ID in the cache entry. Another aspect includes determining whether the determined cache entry is eligible for prefetching. Yet another aspect includes, based on determining that the determined cache entry is eligible for prefetching, setting a marker in the cache entry to active.

## Claims

### Claim 1

A system for thread-based cache content saving for task switching in a computer processor, the system comprising:
a memory; and
the computer processor, communicatively coupled to said memory, the computer system configured to perform a method comprising:
based on a task switch in the computer processor from a first thread to a second thread:
determining a cache entry in a cache of the computer processor that is owned by the first thread, wherein the determination is made based on a hardware thread identifier (ID) of the first thread matching a hardware thread ID in the cache entry;
wherein the hardware thread ID of the first thread comprises an index of a software thread ID of the first thread in a thread ID table of the computer processor, and wherein the thread ID table comprises a list of software thread IDs corresponding to most recently executed threads in the computer processor, wherein each software thread ID in the thread ID table has a corresponding respective index in the thread ID table that comprises a hardware thread ID of a thread corresponding to the software thread ID;
determining whether the determined cache entry is eligible for prefetching; and
based on determining that the determined cache entry is eligible for prefetching, setting a marker in the cache entry to active.

### Claim 2 (depends on 1)

The computer system of claim 1, the method further comprising:
selecting a cache entry from the cache for eviction;
determining whether the hardware thread ID of the selected cache entry is not equal to a hardware thread ID of the second thread;
determining whether the marker of the selected cache entry is set to active; and
based on determining that the hardware thread ID of the selected cache entry is not equal to the hardware thread ID of the second thread and that the marker of the selected cache entry is set to active, saving an address of the selected cache entry to a staging buffer.

### Claim 3 (depends on 2)

The computer system of claim 2, wherein the computer processor comprises a plurality of staging buffers, wherein each staging buffer corresponds to a respective entry in the thread ID table, and further comprising writing contents of a staging buffer of the plurality of staging buffers to a partition footprint log area (PFLA) storage in a main memory or a higher level cache based on the staging buffer being full.

### Claim 4 (depends on 1)

The computer system of claim 1, the method further comprising, based on the task switch:
determining whether a software thread ID of the second thread matches an entry in the thread ID table;
based on determining that the software thread ID of the second thread matches an entry in the thread ID table, setting an active hardware thread ID of the computer processor equal to an index of the determined cache entry in the thread ID table; and
based on determining that the software thread ID of the second thread does not match any entry in the thread ID table:
evicting an entry from the thread ID table;
replacing the evicted entry with a new entry corresponding to the software thread ID of the second thread; and
setting the active hardware thread ID of the computer processor equal to an index of the new entry in the thread ID table.

### Claim 5 (depends on 4)

The computer system of claim 4, further comprising, based on creating a new cache entry during execution of the second thread, setting a hardware thread ID in the new cache entry equal to the active hardware thread ID.

### Claim 6 (depends on 1)

The computer system of claim 1, wherein determining whether the determined cache entry is eligible for prefetching comprises determining a position of the determined cache entry in a least recently used (LRU) stack of the cache.

### Claim 7 (depends on 1)

The computer system of claim 1, wherein determining whether the determined cache entry is eligible for prefetching comprises determining a frequency of usage of the determined cache entry based on a frequency counter that is associated with the determined cache entry.