# US 9,436,477 B2 · Transaction abort instruction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,477 B2 - Document ID: US9436477B2 - Status: Granted - Kind: B2 - Application number: 13/524,855 - Filed: 2012-06-15 - Published: 2013-12-19 - Granted: 2016-09-06 - Earliest claimed: 2012-06-15 - Assignees: International Business Machines Corporation - Applicants: Dan F. Greiner; Christian Jacobi; Marcel M. Mitran; Timothy J. Slegel - Inventors: Dan F. Greiner; Christian Jacobi; Marcel M. Mitran; Timothy J. Slegel - Web page: https://patentgrep.com/patent/US9436477B2 ## CPC - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F 9/30087: {Synchronisation or serialisation instructions} - G06F 9/30101: {Special purpose registers} - G06F 9/3834: {Maintaining memory consistency} - G06F 9/38585: {with result invalidation, e.g. nullification} - G06F 9/3863: {using multiple copies of the architectural state, e.g. shadow registers} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended. ## Claims ### Claim 1 A computer program product for executing an instruction within a computing environment, said computer program product comprising: a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising: an operation code to specify a transaction abort operation; and at least one field to be used to create an address, the address being an abort code, wherein the abort code is formed from at least one value stored in at least one of: one or more fields of the at least one field or one or more locations specified by one or more fields of the at least one field, wherein the at least one field comprises a base field and a displacement field, and wherein based on the base field being nonzero, combining contents of a register specified by the base field and a value of the displacement field to create the abort code; and executing, by the processor, the machine instruction, the executing comprising: aborting a transaction that is executing, wherein the transaction ends prior to completion; and based on the aborting, providing a condition code, the condition code to indicate whether re-execution of the transaction is recommended, and wherein the condition code is based on the abort code. ### Claim 2 (depends on 1) The computer program product of claim 1, wherein the combining comprises adding the contents of the register with the value of the displacement field to create a user-defined abort code. ### Claim 3 (depends on 1) The computer program product of claim 1, wherein based on the base field being zero, the at least one field to specify the abort code consists of the displacement field, and wherein a value of the displacement field specifies the abort code. ### Claim 4 (depends on 1) The computer program product of claim 1, wherein the abort code provides a user-defined specific reason for aborting, and wherein the machine instruction is a transaction abort instruction obtained from a program address specified by a machine program status word (PSW), and wherein the method further comprises: subsequent to executing the machine instruction, replacing the program address of the machine PSW with another program address obtained from a separate and distinct transaction PSW; and continuing execution of instructions beginning with an instruction at the other program address of the machine PSW. ### Claim 5 (depends on 1) The computer program product of claim 1, wherein the condition code comprises a first value based on a specified bit of the abort code being one value, and a second value based on the specified bit being another value. ### Claim 6 (depends on 5) The computer program product of claim 5, wherein the first value indicates re-execution is recommended and the second value indicates re-execution is not recommended. ### Claim 7 (depends on 1) The computer program product of claim 1, wherein the method further comprises placing the abort code in a transaction diagnostic block. ### Claim 8 (depends on 7) The computer program product of claim 7, wherein the transaction diagnostic block is specified by one of an instruction that initiated the transaction being aborted, or an instruction that initiated another transaction, in which the transaction and the other transaction are nested. ### Claim 9 (depends on 1) The computer program product of claim 1, wherein the method further comprises based on aborting the transaction, committing to memory non-transactional store accesses and discarding transactional store accesses. ### Claim 10 A computer system for executing an instruction within a computing environment, said computer system comprising: a memory; and a processor in communications with the memory, the processor including one or more hardware components, and wherein the computer system is configured to perform a method, the method comprising: obtaining, by the processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising: an operation code to specify a transaction abort operation; and at least one field to be used to create an address, the address being an abort code, wherein the abort code is formed from at least one value stored in at least one of: one or more fields of the at least one field or one or more locations specified by one or more fields of the at least one field, wherein the at least one field comprises a base field and a displacement field, and wherein based on the base field being nonzero, combining contents of a register specified by the base field and a value of the displacement field to create the abort code; and executing, by the processor, the machine instruction, the executing comprising: aborting a transaction that is executing, wherein the transaction ends prior to completion; and based on the aborting, providing a condition code, the condition code to indicate whether re-execution of the transaction is recommended, and wherein the condition code is based on the abort code. ### Claim 11 (depends on 10) The computer system of claim 10, wherein the combining comprises adding the contents of the register with the value of the displacement field to create a user-defined abort code. ### Claim 12 (depends on 10) The computer system of claim 10, wherein based on the base field being zero, the at least one field to specify the abort code consists of the displacement field, and wherein a value of the displacement field specifies the abort code. ### Claim 13 (depends on 10) The computer system of claim 10, wherein the condition code comprises a first value based on a specified bit of the abort code being one value, and a second value based on the specified bit being another value. ### Claim 14 (depends on 13) The computer system of claim 13, wherein the first value indicates re-execution is recommended and the second value indicates re-execution is not recommended. ### Claim 15 (depends on 10) The computer system of claim 10, wherein the method further comprises placing the abort code in a transaction diagnostic block. ### Claim 16 (depends on 15) The computer system of claim 15, wherein the transaction diagnostic block is specified by one of an instruction that initiated the transaction being aborted, or an instruction that initiated another transaction, in which the transaction and the other transaction are nested. ### Claim 17 (depends on 10) The computer system of claim 10, wherein the abort code provides a user-defined specific reason for aborting, and wherein the machine instruction is a transaction abort instruction obtained from a program address specified by a machine program status word (PSW), and wherein the method further comprises: subsequent to executing the machine instruction, replacing the program address of the machine PSW with another program address obtained from a separate and distinct transaction PSW; and continuing execution of instructions beginning with an instruction at the other program address of the machine PSW. ### Claim 18 (depends on 10) The computer system of claim 10, wherein the method further comprises based on aborting the transaction, committing to memory non-transactional store accesses and discarding transactional store accesses.