# US 9,436,475 B2 · System and method for executing sequential code using a group of threads and single-instruction, multiple-thread processor incorporating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,475 B2 - Document ID: US9436475B2 - Status: Granted - Kind: B2 - Application number: 13/723,981 - Filed: 2012-12-21 - Published: 2014-05-08 - Granted: 2016-09-06 - Earliest claimed: 2012-11-05 - Assignees: NVIDIA Corporation - Applicants: Nvidia Corporation - Inventors: Gautam Chakrabarti; Yuan Lin; Jaydeep Marathe; Okwan Kwon; Amit Sabne - Web page: https://patentgrep.com/patent/US9436475B2 ## CPC - G06F 9/38: Concurrent instruction execution, e.g. pipeline or look ahead - G06F 8/40: Transformation of program code - G06F 9/30134: {Register stacks; shift registers} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel} - G06F 9/5016: {the resource being the memory} - G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores - G06F 9/522: {Barrier synchronisation} - G06F 12/02: Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) - G06F 12/0853: Cache with multiport tag or data arrays - G06F 2212/451: Stack data - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system and method for executing sequential code in the context of a single-instruction, multiple-thread (SIMT) processor. In one embodiment, the system includes: (1) a pipeline control unit operable to create a group of counterpart threads of the sequential code, one of the counterpart threads being a master thread, remaining ones of the counterpart threads being slave threads and (2) lanes operable to: (2a) execute certain instructions of the sequential code only in the master thread, corresponding instructions in the slave threads being predicated upon the certain instructions and (2b) broadcast branch conditions in the master thread to the slave threads. ## Claims ### Claim 1 A system for executing sequential code, comprising: a pipeline control unit configured to create a group of counterpart threads of said sequential code in a single instruction, multiple thread (SIMT) processor, one of said counterpart threads being a master thread, remaining ones of said counterpart threads being slave threads; and lanes configured to: execute certain instructions of said sequential code only in said master thread, corresponding instructions in said slave threads being predicated upon said certain instructions, and broadcast branch conditions in said master thread to said slave threads, wherein all of said lanes of said SIMT processor execute in lock-step. ### Claim 2 (depends on 1) The system as recited in claim 1 wherein local memories associated with lanes executing said slave threads are further configured to store said branch conditions. ### Claim 3 (depends on 1) The system as recited in claim 1 wherein said certain instructions are selected from the group consisting of: load instructions, store instructions, and exception inducing instructions. ### Claim 4 (depends on 1) The system as recited in claim 1 wherein a lane executing said master thread is further configured to broadcast said branch conditions before execution of a branch instruction in said master thread and lanes executing said slave threads further configured to execute corresponding branch instructions in said slave threads only after said lane broadcasts said branch conditions. ### Claim 5 (depends on 1) The system as recited in claim 1 wherein said pipeline control unit is further configured to predicate said corresponding instructions using a condition based on a thread identifier. ### Claim 6 (depends on 1) The system as recited in claim 1 wherein said sequential code is part of a vector operation. ### Claim 7 A method of executing sequential code, comprising: creating a group of counterpart threads of said sequential code in a single instruction, multiple thread (SIMT) processor, one of said counterpart threads being a master thread, remaining ones of said counterpart threads being slave threads; executing certain instructions of said sequential code only in said master thread, corresponding instructions in said slave threads being predicated upon said certain instructions; and broadcasting branch conditions in said master thread to said slave threads, wherein lanes of said SIMT processor execute in lock-step. ### Claim 8 (depends on 7) The method as recited in claim 7 further comprising storing said branch conditions in local memories associated with said slave threads. ### Claim 9 (depends on 7) The method as recited in claim 7 wherein said certain instructions are selected from the group consisting of: load instructions, store instructions, and exception inducing instructions. ### Claim 10 (depends on 7) The method as recited in claim 7 wherein said broadcasting is carried out before execution of a branch instruction in said master thread, said method further comprising: executing corresponding branch instructions in said slave threads only after said broadcasting is carried out. ### Claim 11 (depends on 7) The method as recited in claim 7 wherein said executing comprises predicating said corresponding instructions using a condition based on a thread identifier. ### Claim 12 (depends on 7) The method as recited in claim 7 wherein said sequential code is part of a vector operation. ### Claim 13 A single-instruction, multiple-thread (SIMT) processor, comprising: lanes; local memories associated with corresponding ones of said lanes; shared memory device by said lanes; and a pipeline control unit configured to create a group of counterpart threads of said sequential code and cause said group to be executed in said lanes, one of said counterpart threads being a master thread, remaining ones of said counterpart threads being slave threads, said lanes configured to: execute certain instructions of said sequential code only in said master thread, corresponding instructions in said slave threads being predicated upon said certain instructions, and broadcast branch conditions in said master thread to said slave threads, wherein all of said lanes operate of said SIMT processor execute in lock-step. ### Claim 14 (depends on 13) The SIMT processor as recited in claim 13 wherein said local memories associated with lanes executing said slave threads are further configured to store said branch conditions. ### Claim 15 (depends on 13) The SIMT processor as recited in claim 13 wherein said certain instructions are selected from the group consisting of: load instructions, store instructions, and exception inducing instructions. ### Claim 16 (depends on 13) The SIMT processor as recited in claim 13 wherein a lane executing said master thread is further configured to broadcast said branch conditions before execution of a branch instruction in said master thread and lanes executing said slave threads further configured to execute corresponding branch instructions in said slave threads only after said lane broadcasts said branch conditions. ### Claim 17 (depends on 13) The SIMT processor as recited in claim 13 wherein said pipeline control unit is further configured to predicate said corresponding instructions using a condition based on a thread identifier.