# US 9,436,471 B2 · Efficient recording and replaying of non-deterministic instructions in a virtual machine and CPU therefor

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- Number: US 9,436,471 B2
- Document ID: US9436471B2
- Status: Granted
- Kind: B2
- Application number: 13/926,605
- Filed: 2013-06-25
- Published: 2013-10-31
- Granted: 2016-09-06
- Earliest claimed: 2008-07-03
- Assignees: VMware, Inc.
- Applicants: VMware, Inc.
- Inventors: Vyacheslav V. Malyugin; Min Xu; Boris Weissman; Ganesh Venkitachalam; Alexander Klaiber
- Web page: https://patentgrep.com/patent/US9436471B2

## CPC

- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/3005: {to perform operations for flow control}
- G06F 9/323: {for indirect branch instructions}
- G06F 11/301: {where the computing system is a virtual computing platform, e.g. logically partitioned systems (virtual machines G06F9/45533; logical partitioning of resources G06F9/5077)}
- G06F 11/3024: {where the computing system component is a central processing unit [CPU]}
- G06F 11/3414: {Workload generation, e.g. scripts, playback}
- G06F 11/3476: {Data logging (G06F11/14, G06F11/2205 take precedence)}
- G06F 9/45533: {Hypervisors; Virtual machine monitors}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The output of a non-deterministic instruction is handled during record and replay in a virtual machine. An output of a non-deterministic instruction is stored to a buffer during record mode and retrieved from a buffer during replay mode without exiting to the hypervisor. At least part of the contents of the buffer can be stored to a log when the buffer is full during record mode, and the buffer can be replenished from a log when the buffer is empty during replay mode.

## Claims

### Claim 1

A CPU having operational modes comprising at least a normal mode, a record mode, and a replay mode, wherein:
the CPU is configured such that when the CPU is in the record mode, each time an instruction included in a predefined subset of an instruction set of the CPU is executed in a virtual computing instance, a result of execution of the instruction is stored in a buffer without a context switch to a virtualization software hosting the virtual computing instance, the CPU triggering a fault or exception to perform the context switch and move contents of the buffer into a log file that is accessible by the virtualization software when the buffer is full; and
the CPU is further configured such that when the CPU is in the replay mode, each time the instruction included in the predefined subset is executed, a next non-deterministic value is read from the buffer without a context switch to the virtualization software and supplied in place of a result of the execution of the instruction, the CPU triggering a fault or exception to perform the context switch to the virtualization software and move contents of the log file into the buffer, when the buffer does not contain the next non-deterministic value;
wherein the predefined subset comprises instructions that generate non-deterministic values.

### Claim 2 (depends on 1)

The CPU of claim 1, wherein the operational mode of the CPU depends on a value of at least two data bits residing in at least one machine specific register.

### Claim 3 (depends on 1)

The CPU of claim 1, wherein the operational mode of the CPU depends on a value of at least two data bits within a data structure, the data bits being accessible by a privileged process.

### Claim 4 (depends on 3)

The CPU of claim 3, wherein the data bits are located in machine memory, the machine memory being accessible by the CPU via a data bus.

### Claim 5 (depends on 3)

The CPU of claim 3, wherein the virtual computing instance is a guest virtual machine and the data bits define a mode of the guest virtual machine from which the instruction originates.

### Claim 6 (depends on 1)

The CPU of claim 1, wherein the operational mode of the CPU is changed by issuing a machine-specific instruction to the CPU.

### Claim 7 (depends on 1)

The CPU of claim 1, wherein the buffer resides on the CPU.

### Claim 8 (depends on 1)

The CPU of claim 1, wherein the buffer resides in machine memory in communication with the CPU over a data bus.

### Claim 9 (depends on 8)

The CPU of claim 8, wherein the virtual computing instance is a guest virtual machine and the machine memory is addressed by virtual addresses within a virtual address space of the guest virtual machine from which the instruction originates.