# US 9,436,435 B2 · Apparatus and method for vector instructions for large integer arithmetic > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,435 B2 - Document ID: US9436435B2 - Status: Granted - Kind: B2 - Application number: 13/996,529 - Filed: 2011-12-23 - Published: 2014-06-12 - Granted: 2016-09-06 - Earliest claimed: 2011-12-23 - Assignees: Intel Corporation - Applicants: Gilbert M. Wolrich; Kirk S. Yap; James D. Guilford; Erdinc Ozturk; Vinodh Gopal; Wajdi K. Feghali; Sean M. Gulley; Martin G. Dixon - Inventors: Gilbert M. Wolrich; Kirk S. Yap; James D. Guilford; Erdinc Ozturk; Vinodh Gopal; Wajdi K. Feghali; Sean M. Gulley; Martin G. Dixon - Web page: https://patentgrep.com/patent/US9436435B2 ## CPC - G06F 9/3016: {Decoding the operand specifier, e.g. specifier format} - G06F 7/525: in serial-serial fashion, i.e. both operands being entered serially (G06F7/533 takes precedence) - G06F 7/57: Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} - G06F 9/3001: {Arithmetic instructions} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/3893: {controlled in tandem, e.g. multiplier-accumulator} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register. ## Claims ### Claim 1 A method comprising: decoding a first instruction, a second instruction, a third instruction, a fourth instruction, and a fifth instruction with a hardware decoder of a hardware processor; executing the first instruction with a hardware execution unit of the hardware processor to multiply a first input operand and a second input operand and present a lower portion of a result, said first input operand representing a first digit of a multiplier, said second input operand representing a first digit of a multiplicand; executing the second instruction with the hardware execution unit of the hardware processor to multiply said first input operand and said second input operand and present an upper portion of a result; executing the third instruction with the hardware execution unit of the hardware processor to multiply said first input operand and a third input operand and present a lower portion of a result, said third input operand representing a digit of said multiplicand that neighbors said first digit of said multiplicand; executing the fourth instruction with the hardware execution unit of the hardware processor to multiply said first input operand and said third input operand and present an upper portion of a result; and executing the fifth instruction with the hardware execution unit of the hardware processor to add aligned digits of the upper and lower portions and record a carry term in a mask register. ### Claim 2 (depends on 1) The method of claim 1 wherein the first and second instructions are executed in a same recursion. ### Claim 3 (depends on 1) The method of claim 1 wherein a multiplexer of said hardware execution unit of the hardware processor is to output a low half from a multiplier for the first instruction and a high half from the multiplier for the second instruction. ### Claim 4 (depends on 1) The method of claim 1 wherein the carry term is one of a plurality of carry terms that are separately tracked in mask register space. ### Claim 5 (depends on 1) The method of claim 1 wherein said executing the fifth instruction with the hardware execution unit of the hardware processor is to also add in an input carry term from the mask register. ### Claim 6 (depends on 1) The method of claim 1 wherein the carry term is more than one bit. ### Claim 7 (depends on 6) The method of claim 6 wherein said carry term is written as least significant bits of a next higher ordered accumulated partial product term. ### Claim 8 A hardware processor comprising: a hardware decoder to decode a first instruction, a second instruction, and an add instruction; and a hardware execution unit to: execute the first instruction to multiply a first input operand and a second input operand and present a lower portion of a result, said first and second input operands being respective elements of first and second input vectors, execute the second instruction to multiply the first input operand and the second input operand and present an upper portion of a result, said first and second input operands being respective elements of first and second input vectors, and execute the add instruction that is to add aligned digits of the upper and lower portions and cause a carry term of said add instruction's adding to be recorded in a mask register. ### Claim 9 (depends on 8) The hardware processor of claim 8 wherein said add instruction comprises an operand to identify the mask register. ### Claim 10 (depends on 8) The hardware processor of claim 8 wherein the carry term is a plurality of bits. ### Claim 11 (depends on 8) The hardware processor of claim 8 wherein said add instruction accepts an input carry term through said mask register. ### Claim 12 (depends on 11) The hardware processor of claim 11 wherein said add instruction writes said input carry term as least significant bits of its add resultant. ### Claim 13 (depends on 8) The hardware processor of claim 8 wherein a multiplexer of said hardware execution unit is to output a low half from a multiplier for the first instruction and a high half from the multiplier for the second instruction. ### Claim 14 (depends on 8) The hardware processor of claim 8 wherein said first and second instructions are vector instructions that multiply respective elements of first and second input vectors, said first input operand being an element of said first input vector and said second input operand being an element of a second input vector. ### Claim 15 (depends on 8) The hardware processor of claim 8, wherein the carry term is one of a plurality of carry terms that are separately tracked in mask register space. ### Claim 16 A non-transitory machine readable medium containing program code that when processed by a processing unit causes a method to be performed, said method comprising: decoding a first instruction, a second instruction, a third instruction, a fourth instruction, and a fifth instruction with a hardware decoder of a hardware processor; executing the first instruction with a hardware execution unit of the hardware processor to multiply a first input operand and a second input operand and present a lower portion of a result, said first input operand representing a first digit of a multiplier, said second input operand representing a first digit of a multiplicand; executing the second instruction with the hardware execution unit of the hardware processor to multiply said first input operand and said second input operand and present an upper portion of a result; executing the third instruction with the hardware execution unit of the hardware processor to multiply said first input operand and a third input operand and present a lower portion of a result, said third input operand representing a digit of said multiplicand that neighbors said first digit of said multiplicand; executing the fourth instruction with the hardware execution unit of the hardware processor to multiply said first input operand and said third input operand and present an upper portion of a result; and executing the fifth instruction with the hardware execution unit of the hardware processor to add aligned digits of the upper and lower portions and record a carry term in a mask register. ### Claim 17 (depends on 16) The non-transitory machine readable medium of claim 16 wherein the first and second instructions are executed in a same recursion. ### Claim 18 (depends on 16) The non-transitory machine readable medium of claim 16 wherein a multiplexer of said hardware execution unit of the hardware processor is to output a low half from a multiplier for the first instruction and a high half from the multiplier for the second instruction. ### Claim 19 (depends on 16) The non-transitory machine readable medium of claim 16 wherein the carry term is one of a plurality of carry terms that are separately tracked in mask register space. ### Claim 20 (depends on 16) The non-transitory machine readable medium of claim 16 wherein said executing the fifth instruction with the hardware execution unit of the hardware processor is to also add in an input carry term from the mask register. ### Claim 21 (depends on 16) The non-transitory machine readable medium of claim 16 wherein the carry term is more than one bit. ### Claim 22 (depends on 21) The non-transitory machine readable medium of claim 21 wherein said carry term is an input carry term and said input carry term is written as least significant bits of said adding's resultant.