# US 9,436,434 B2 · Checksum adder > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,434 B2 - Document ID: US9436434B2 - Status: Granted - Kind: B2 - Application number: 14/211,383 - Filed: 2014-03-14 - Published: 2015-09-17 - Granted: 2016-09-06 - Earliest claimed: 2014-03-14 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: James R. Cuffney; John G. Rell, Jr.; Eric M. Schwarz; Patrick M. West, Jr. - Web page: https://patentgrep.com/patent/US9436434B2 ## CPC - G06F 7/5016: {forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels} - G06F 7/50: Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) - H03M 7/30: Compression (speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N); Expansion; Suppression of unnecessary data, e.g. redundancy reduction - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Embodiments relate to a hardware circuit that is operable as a fixed point adder and a checksum adder. An aspect includes a driving of a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition and a driving of a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition. ## Claims ### Claim 1 A computer system for executing multiple functions, the system comprising: a memory; and a processor, communicatively coupled to said memory, the computer system configured to perform a method comprising: driving, by the processor, a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition; and driving, by the processor, a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition. ### Claim 2 (depends on 1) The system according to claim 1, wherein the first and second schemes of vector input addition respectively comprise fixed point addition and checksum addition. ### Claim 3 (depends on 2) The system according to claim 2, wherein the control bit signals whether fixed point addition or checksum addition is to be executed and performed. ### Claim 4 (depends on 1) The system according to claim 1, wherein the multifunction compression tree comprises n bit circuits arranged in a sequence, wherein n≧3, a lowest numbered bit circuit is bit0 and a highest numbered bit circuit is bitn−1. ### Claim 5 (depends on 4) The system according to claim 4, wherein the driving of the multifunction compression tree comprises: receiving at a zeroth level compressor of each bit circuit an input of three vector inputs and outputting from the zeroth level compressor a zeroth level carryout and a zeroth level sum; receiving at a first level compressor of each bit circuit an input of two vector inputs and a first level carry-in derived from a zeroth level carry-out of an adjacent, higher numbered bit circuit and outputting from the first level compressor a first level carry-out and a first level sum; and receiving at a second level compressor of each bit circuit an input of the zeroth level and first level sums and a second level carry-in derived from a first level carry-out of the adjacent, higher numbered bit circuit and outputting from the second level compressor a carry term and a sum term. ### Claim 6 (depends on 5) The system according to claim 5, wherein the driving of the multifunction compression tree further comprises: ANDing the control bit along with the zeroth level carry-out in a first AND Gate disposed between lines respectively associated with the zeroth level carry-out of the bit0 bit circuit and the first level carry-in of the bitn−1 bit circuit; and ANDing the control bit along with the first level carry-out in a second AND Gate disposed between lines respectively associated with the first level carry-out of the bit0 bit circuit and the second level carry-in of the bitn−1 bit circuit. ### Claim 7 (depends on 1) The system according to claim 1, wherein the multifunction adder comprises: a fixed point addition adder; a checksum addition adder disposed in parallel with the fixed point addition adder; and a multiplexer controllable to generate as a result an output of either the fixed point addition adder or the checksum addition adder. ### Claim 8 (depends on 7) The system according to claim 7, wherein the driving of the multifunction adder comprises: receiving an output of the multifunction compression tree at the fixed point addition adder and the checksum addition adder; and controlling the multiplexer based on the control bit to generate as a result an output of either the fixed point addition adder or the checksum addition adder. ### Claim 9 A computer implemented method for implementing multiple functions, the method comprising: driving, by a computer, a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition; and driving, by the computer, a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition. ### Claim 10 (depends on 9) The method according to claim 9, wherein the first and second schemes of vector input addition respectively comprise fixed point addition and checksum addition. ### Claim 11 (depends on 10) The method according to claim 10, wherein the control bit signals whether fixed point addition or checksum addition is to be executed and performed. ### Claim 12 (depends on 9) The method according to claim 9, wherein the multifunction compression tree comprises n bit circuits arranged in a sequence, wherein n≧3, a lowest numbered bit circuit is bit0 and a highest numbered bit circuit is bitn−1. ### Claim 13 (depends on 12) The method according to claim 12, wherein the driving of the multifunction compression tree comprises: receiving at a zeroth level compressor of each bit circuit an input of three vector inputs and outputting from the zeroth level compressor a zeroth level carryout and a zeroth level sum; receiving at a first level compressor of each bit circuit an input of two vector inputs and a first level carry-in derived from a zeroth level carry-out of an adjacent, higher numbered bit circuit and outputting from the first level compressor a first level carry-out and a first level sum; and receiving at a second level compressor of each bit circuit an input of the zeroth level and first level sums and a second level carry-in derived from a first level carry-out of the adjacent, higher numbered bit circuit and outputting from the second level compressor a carry term and a sum term. ### Claim 14 (depends on 13) The method according to claim 13, wherein the driving of the multifunction compression tree further comprises: ANDing the control bit along with the zeroth level carry-out in a first AND Gate disposed between lines respectively associated with the zeroth level carry-out of the bit0 bit circuit and the first level carry-in of the bitn−1 bit circuit; and ANDing the control bit along with the first level carry-out in a second AND Gate disposed between lines respectively associated with the first level carry-out of the bit0 bit circuit and the second level carry-in of the bitn−1 bit circuit. ### Claim 15 (depends on 9) The method according to claim 9, wherein the driving of the multifunction adder comprises: receiving an output of the multifunction compression tree at a fixed point addition adder and a checksum addition adder disposed in parallel; and controlling a multiplexer based on the control bit to generate as a result an output of either the fixed point addition adder or the checksum addition adder. ### Claim 16 A computer program product for implementing multiple functions, the computer program product comprising: a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a signal, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising: driving a multifunction compression tree disposed on a circuit path based on a control bit to execute one of first and second schemes of vector input addition; and driving a multifunction adder disposed on the circuit path based on the control bit to perform the one of the first and second schemes of vector input addition. ### Claim 17 (depends on 16) The computer program product according to claim 16, wherein the first and second schemes of vector input addition respectively comprise fixed point addition and checksum addition, the control bit being configured to signal whether fixed point addition or checksum addition is to be executed and performed. ### Claim 18 (depends on 16) The computer program product according to claim 16, wherein the multifunction compression tree comprises n bit circuits arranged in a sequence, wherein n≧3, a lowest numbered bit circuit is bit0 and a highest numbered bit circuit is bitn−1, the driving of the multifunction compression tree comprising: receiving at a zeroth level compressor of each bit circuit an input of three vector inputs and outputting from the zeroth level compressor a zeroth level carryout and a zeroth level sum; receiving at a first level compressor of each bit circuit an input of two vector inputs and a first level carry-in derived from a zeroth level carry-out of an adjacent, higher numbered bit circuit and outputting from the first level compressor a first level carry-out and a first level sum; and receiving at a second level compressor of each bit circuit an input of the zeroth level and first level sums and a second level carry-in derived from a first level carry-out of the adjacent, higher numbered bit circuit and outputting from the second level compressor a carry term and a sum term. ### Claim 19 (depends on 18) The computer program product according to claim 18, wherein the driving of the multifunction compression tree further comprises: ANDing the control bit along with the zeroth level carry-out in a first AND Gate disposed between lines respectively associated with the zeroth level carry-out of the bit0 bit circuit and the first level carry-in of the bitn−1 bit circuit; and ANDing the control bit along with the first level carry-out in a second AND Gate disposed between lines respectively associated with the first level carry-out of the bit0 bit circuit and the second level carry-in of the bitn−1 bit circuit. ### Claim 20 (depends on 16) The computer program product according to claim 16, wherein the driving of the multifunction adder comprises: receiving an output of the multifunction compression tree at a fixed point addition adder and a checksum addition adder disposed in parallel; and controlling a multiplexer based on the control bit to generate as a result an output of either the fixed point addition adder or the checksum addition adder.