# US 9,436,433 B2 · Method, apparatus and instructions for parallel data conversions

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- Number: US 9,436,433 B2
- Document ID: US9436433B2
- Status: Granted
- Kind: B2
- Application number: 14/700,736
- Filed: 2015-04-30
- Published: 2015-10-22
- Granted: 2016-09-06
- Earliest claimed: 2003-09-08
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Gopalan Ramanujam
- Web page: https://patentgrep.com/patent/US9436433B2

## CPC

- G06F 9/384: {Register renaming}
- G06F 7/48: using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F 9/30014: {with variable precision}
- G06F 9/30025: {Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion}
- G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30109: {having multiple operands in a single register}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/3016: {Decoding the operand specifier, e.g. specifier format}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 15/82: data or demand driven
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

## Claims

### Claim 1

A reduced instruction set computer (RISC) processor comprising:
a register file, within the RISC processor, including a first packed data register and a second packed data register;
register rename logic within the RISC processor;
a decoder, within the RISC processor, to decode instructions, the instructions to include a first instruction;
schedule logic, within the RISC processor, to queue operations that correspond to the instructions for execution; and
execution logic, within the RISC processor, coupled to the decoder, the register rename logic, and the schedule logic, the execution logic to perform out-of-order execution of at least some of the instructions;
wherein, responsive to a decode of the first instruction by the decoder, the execution logic is to convert a first plurality of packed signed data elements to be stored in the first packed data register to a second plurality of packed unsigned data elements in the second packed data register, one or more of the second plurality of packed unsigned data elements to be saturated;
the first plurality of packed signed data elements to include floating point data elements and the second plurality of packed unsigned data elements to include integer data elements;
at least one of the packed signed data elements to have a first number of bits, at least one of the packed unsigned data elements to have a second number of bits, wherein the second number of bits is one half the first number of bits.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the first number of bits is 64 and the second number of bits is 32.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the one or more of the second plurality of packed unsigned data elements is to be saturated if a condition is satisfied.