# US 9,436,432 B2 · First-in first-out (FIFO) memory with multi-port functionality > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,432 B2 - Document ID: US9436432B2 - Status: Granted - Kind: B2 - Application number: 11/648,113 - Filed: 2006-12-29 - Published: 2007-08-09 - Granted: 2016-09-06 - Earliest claimed: 2005-12-30 - Assignees: STMicroelectronics International N.V. - Applicants: Kapil Batra - Inventors: Kapil Batra - Web page: https://patentgrep.com/patent/US9436432B2 ## CPC - G06F 5/065: {Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's} - G06F 5/16: Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers - G11C 7/1075: {for multiport memories each having random access ports and serial ports, e.g. video RAM} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory may require a buffering mechanism in which data can be written and read at the same time. This requires a multi-port FIFO memory, which has multiple ports, thus providing simultaneous read & write operations. Multi-port memories have a large penalty on area. Hence, a technique is proposed for avoiding use of multi-port memories for designs which requires sequential read and write operations. In this technique multiple single-port memories are used to form a multi-port memory. This memory requires additional control logic but consumes significantly lower silicon area. ## Claims ### Claim 1 A first-in first-out (FIFO) memory providing multi-port functionality, the FIFO memory comprising: a plurality of single-port memory structures, each single port memory structure having a plurality of addresses to read and write data thereto; an indexing block configured to store, for each data write operation, a unique memory identifier corresponding to a single-port memory structure in which the data write operation is performed; and an access controller configured to control operations in the single-port memory structures based on contents of the indexing block, wherein the access controller is configured to perform a plurality of write operations to the plurality of single-port memory structures in a single clock cycle, and wherein the access controller is further configured to continue at least one write operation of the plurality of write operations in the single clock cycle to a write address of a different single port memory structure of the plurality of single-port memory structures during the single clock cycle whenever there is a read and write operation request at a same time on one of the plurality of single-port memory structures. ### Claim 2 (depends on 1) The FIFO memory according to claim 1, wherein the access controller, during a write operation, is configured to perform a “read operation active” check to find a free one of the plurality of single-port memory structures to perform the write operation. ### Claim 3 (depends on 1) The FIFO memory according to claim 1, wherein the access controller is configured to store memory information having a read and write pointer for each of the plurality of single-port memory structures and the indexing block. ### Claim 4 (depends on 1) The FIFO memory according to claim 1, wherein the indexing block further comprises: a plurality of flip-flops configured to store unique identification information corresponding to each of the plurality of single-port memory structures. ### Claim 5 (depends on 1) The FIFO memory according to claim 1, wherein the access controller is configured to alternate sequential write operations between the plurality of single-port memory structures. ### Claim 6 (depends on 1) The FIFO memory according to claim 1, wherein the access controller, during a read operation from a single-port memory structure, is configured to enable a “read operation active” flag to indicate unavailability of the single-port memory structure for a write operation. ### Claim 7 (depends on 1) The FIFO memory of claim 1, wherein the access controller is configured to: perform a “busy due to ongoing read” check before every write on memory required for a write operation request. ### Claim 8 (depends on 1) The FIFO memory of claim 1, wherein the FIFO memory is configured to emulate a dual-port FIFO memory of size N×M with two single-port memory structures of size N/2×M. ### Claim 9 A method of operating a plurality of single-port memory structures as a multi-port first-in first-out (FIFO) memory for sequential memory operations, each single-port memory structure having a plurality of addresses to read and write data thereto, the method comprising: maintaining a unique identifier corresponding to each of the single-port memory structure; for each of a plurality of data write operations to the FIFO memory in a single clock cycle: performing a “read operation active” check to find which of the plurality of single-port memory structures is free for the data write operations, and storing the unique identifier corresponding to the single-port memory structure in which a data write operation is done in an indexing block, wherein the indexing block stores K×N bits, where K bits are required for storing the unique identifier of a single-port memory structure and the multi-port FIFO memory has N locations; performing data read operations at a same time sequential with the data write operations based on the contents of the indexing block to ascertain the single-port memory structure which has to be read, wherein during the read operation a “read operation active” flag is enabled to indicate unavailability of the single-port memory structure for the data write operation; and continuing at least one data write operation of the plurality of data write operations in the single clock cycle to a write address of a different single-port memory structure of the plurality of single-port memory structures whenever there is a read and write operation request at a same time on one of the plurality of single-port memory structures during the single clock cycle. ### Claim 10 (depends on 9) The method according to claim 9, wherein the indexing block further comprising: storing unique identification information corresponding to each of the plurality of single-port memory structures within a plurality of flip-flops. ### Claim 11 (depends on 9) The method according to claim 9 further comprising: alternating the sequential write operations between the plurality of single-port memory structures. ### Claim 12 (depends on 9) The method according to claim 9, further comprising storing a read and write pointer for each of the plurality of single-port memory structures and the indexing block. ### Claim 13 A first-in first-out (FIFO) memory structure providing multi-port functionality for a FIFO queue, the FIFO memory structure comprising: a plurality of single-port memory structures, each single port memory structure having a plurality of addresses to read and write data thereto; an access controller configured to maintain pointer information for read and write operations in the plurality of single-port memory structures; and an indexing block configured to store a unique memory identifier corresponding to a single-port memory structure in which a data write operation is performed, wherein the access controller is configured to perform a plurality of write operations to the plurality of single-port memory structures in a single clock cycle, and wherein the access controller is further configured to continue at least one write operation of the plurality of write operations in the single clock cycle to a write address of a different single port memory structure of the plurality of single-port memory structures during the single clock cycle whenever there is a read and write operation request at a same time on one of the plurality of single-port memory structures. ### Claim 14 (depends on 13) The FIFO memory according to claim 13, wherein the access controller, during a write operation, is configured to perform a “read operation active” check to find a free one of the plurality of single-port memory structures to perform the write operation. ### Claim 15 (depends on 13) The FIFO memory according to claim 13, wherein the access controller is configured to store memory information comprising a read and write pointer for each of the plurality of single-port memory structures and the indexing block. ### Claim 16 (depends on 13) The FIFO memory according to claim 13, wherein the indexing block further comprises: a plurality of flip-flops configured to store the unique memory identifier corresponding to each of the plurality of single-port memory structures. ### Claim 17 (depends on 13) The FIFO memory according to claim 13, wherein sequential write operations are alternated between the plurality of single-port memory structures. ### Claim 18 (depends on 13) The FIFO memory according to claim 13, wherein the access controller, during a read operation from a single-port memory structure, is configured to enable a “read operation active” flag to indicate unavailability of the single-port memory structure for a write operation.