# US 9,436,398 B2 · Memory interface supporting both ECC and per-byte data masking

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- Number: US 9,436,398 B2
- Document ID: US9436398B2
- Status: Granted
- Kind: B2
- Application number: 14/728,438
- Filed: 2015-06-02
- Published: 2015-09-17
- Granted: 2016-09-06
- Earliest claimed: 2012-12-20
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: James O'Connor; Warren Kruger
- Web page: https://patentgrep.com/patent/US9436398B2

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 11/1052: {Bypassing or disabling error detection or correction}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1009: {Data masking during input/output}
- G11C 29/76: {using address translation or modifications}
- G11C 2029/0411: {Online error correction}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked according to a first input. The logic, in response to a second command, writes data into the data bits of the memory block and writes a second input into the additional bits of the memory block.

## Claims

### Claim 1

A system, comprising:
a processor; and
a memory;
wherein the memory is communicatively connected to the processor by a memory bus channel;
wherein the memory comprises:
a memory block comprising data bits and additional bits; and
logic configured to:
receive a first and a second input;
mask data in response to the first input;
respond to a first command, wherein the response includes:
writing the masked data into the data bits of the memory block, and writing “don't care” values into the additional bits of the memory block; and
respond to a second command, wherein the response includes:
writing the data into the data bits of the memory block, and
writing the second input into the additional bits of the memory block.

### Claim 2 (depends on 1)

The system of claim 1, further comprising a memory controller;
wherein the memory controller is communicatively connected to the processor and the memory;
wherein the memory controller is configured to send the first command and second command to the memory.

### Claim 3 (depends on 2)

The system of claim 2, wherein the logic is further configured to transmit signals to the memory controller.

### Claim 4 (depends on 2)

The system of claim 2, wherein the memory controller is integral to the processor.

### Claim 5 (depends on 1)

The system of claim 1, wherein the memory channel bus is a physical interface.

### Claim 6 (depends on 5)

The system of claim 5, wherein the physical interface is a socket.

### Claim 7 (depends on 1)

The system of claim 1, wherein the response to the first command further includes writing a per-byte parity bit into the additional bits.

### Claim 8 (depends on 1)

The system of claim 1, wherein the data is masked according to a per-byte bit mask.

### Claim 9 (depends on 1)

The system of claim 1, wherein the logic is further configured to respond to a third command, wherein the response includes:
outputting the data from the data bits and the additional bits.

### Claim 10 (depends on 1)

The system of claim 1, wherein the memory further comprises a mode bit, and wherein the first command comprises a write command when the mode bit is set to a first value, and wherein the second command comprises the write command when the mode bit set to a second value.