# US 9,436,388 B2 · Memory access alignment in a double data rate (‘DDR’) system

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- Number: US 9,436,388 B2
- Document ID: US9436388B2
- Status: Granted
- Kind: B2
- Application number: 15/093,063
- Filed: 2016-04-07
- Published: 2016-07-28
- Granted: 2016-09-06
- Earliest claimed: 2011-06-29
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Steven K. Jenkins; Robert B. Likovich, Jr.; Michael R. Trombley
- Web page: https://patentgrep.com/patent/US9436388B2

## CPC

- G06F 3/0605: {by facilitating the interaction with a user or administrator}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0673: {Single storage device}
- G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06)
- G11C 7/1066: {Output synchronization}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/1093: {Input synchronization}
- G11C 11/40622: {Partial refresh of memory arrays}
- G11C 29/022: {in I/O circuitry}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 11/40: using transistors
- G11C 2207/2254: Calibration
- G11C 2207/2272: Latency related aspects
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.

## Claims

### Claim 1

An apparatus for memory access alignment in a double data rate (‘DDR’) system, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the processor, cause the apparatus to carry out the steps of:
executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module;
executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module; and
determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.

### Claim 2 (depends on 1)

The apparatus of claim 1 wherein executing, by a memory controller, one or more write operations to a predetermined address of the DDR memory module further comprises:
determining, by the memory controller, the burst length for the write operations, the burst length comprising the number of bytes that are to be written to an address in response to a single write command; and
determining, by the memory controller, a number of write operations to execute in dependence upon the burst length.

### Claim 3 (depends on 1)

The apparatus of claim 1 further comprising computer program instructions that, when executed by the processor, cause the apparatus to carry out the steps of:
storing, by the memory controller, the read adjust value; and
increasing, by the read adjust value, the number of cycles between signaling a subsequent read operation and capturing data from the subsequent read operation.

### Claim 4 (depends on 1)

The apparatus of claim 1 further comprising computer program instructions that, when executed by the processor, cause the apparatus to carry out the steps of:
storing, by the memory controller, the write adjust value; and
increasing, by the write adjust value, the number of cycles between signaling the DDR memory module of a subsequent write operation and sending to the DDR memory module data associated with the subsequent write operation along with the data strobe signal.

### Claim 5 (depends on 1)

The apparatus of claim 1 wherein the predetermined pattern is characterized by incrementally increasing numerical values.

### Claim 6 (depends on 1)

The apparatus of claim 1 wherein:
executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module includes executing only a single write operation;
sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal includes sending two burst lengths of data; and
capturing data transmitted from the DDR memory module includes capturing only one burst length of data.

### Claim 7 (depends on 1)

The apparatus of claim 1 wherein the predetermined pattern includes numerical values from 0 to 7 organized incrementally.

### Claim 8 (depends on 1)

The apparatus of claim 1 wherein determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations includes:
determining, whether a numerical value in a first unit of the captured data is greater than a numerical value in a second unit of the captured data;
responsive to determining that the numerical value in the first unit of the captured data is greater than the numerical value in the second unit of the captured data, setting the read adjust value to one and setting the write adjust value to the numerical value in the second unit of the captured data;
determining, whether the numerical value in a second unit of the captured data is greater than a numerical value in a third unit of the captured data;
responsive to determining that the numerical value in the second unit of the captured data is greater than the numerical value in the third unit of the captured data, setting the read adjust value to two and setting the write adjust value to the numerical value in the third unit of the captured data;
determining, whether the numerical value in a third unit of the captured data is greater than a numerical value in a fourth unit of the captured data; and
responsive to determining that the numerical value in the third unit of the captured data is greater than the numerical value in the fourth unit of the captured data, setting the read adjust value to three and setting the write adjust value to the numerical value in the fourth unit of the captured data, otherwise setting the read adjust value to zero and setting the write adjust value to the numerical value in the first unit of the captured data.

### Claim 9 (depends on 1)

The apparatus of claim 1 wherein executing the one or more write operations to the predetermined address of the DDR memory module further comprises signaling the DDR memory module of the one or more write operations and sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal.

### Claim 10 (depends on 1)

The apparatus of claim 1 wherein executing the plurality of read operations from the predetermined address of the DDR memory module further comprises signaling the DDR memory module of the read operations and capturing data transmitted from the DDR memory module.

### Claim 11 (depends on 1)

The apparatus of claim 1 wherein the read adjust value comprises a number of cycles between signaling the read operations and capturing the data, and wherein the write adjust value comprises a number of cycles between signaling the DDR memory module of the one or more write operations and sending to the DDR memory module the predetermined amount of data of the predetermined pattern along with the data strobe signal.