# US 9,436,265 B2 · Information processing apparatus and load control method

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- Number: US 9,436,265 B2
- Document ID: US9436265B2
- Status: Granted
- Kind: B2
- Application number: 14/062,260
- Filed: 2013-10-24
- Published: 2015-04-30
- Granted: 2016-09-06
- Earliest claimed: 2013-10-24
- Assignees: Fujitsu Limited; Georgia Tech Research Corporation
- Applicants: Fujitsu Limited; The Georgia Tech Research Corporation
- Inventors: Yasuhiko Kanemasa; Qingyang Wang; Calton Pu
- Web page: https://patentgrep.com/patent/US9436265B2

## CPC

- G06F 1/324: by lowering clock frequency
- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 1/3228: Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An information processing apparatus includes a processor that is capable of switching a performance level to one of a plurality of performance levels with different power consumption, and a storage unit that stores a program for controlling the performance level of the processor. The processor executing the program detects the periodicity of load variation of the information processing apparatus, and changes, according to the periodicity of the load variation, a determination interval for determining whether to switch the performance level of the processor.

## Claims

### Claim 1

An information processing apparatus comprising:
at least one processor configured to be capable of switching a performance level to one of a plurality of performance levels with different power consumption; and
a storage unit configured to store a program for controlling the performance level of the at least one processor, wherein
the at least one processor executing the program performs a procedure including:
detecting times when the performance level of the processor was increased from a first level to a second level, the first level being lower than a threshold, the second level being equal to or greater than the threshold;
calculating an average time period between the detected times; and
changing, according to the calculated average time period, a determination interval for determining whether to switch the performance level of the processor.

### Claim 2 (depends on 1)

The information processing apparatus according to claim 1, wherein the determination interval is shorter than the average time period.

### Claim 3 (depends on 1)

The information processing apparatus according to claim 1, wherein the procedure further includes preventing shortening of the determination interval upon determining that the detected times have no periodicity.

### Claim 4 (depends on 1)

The information processing apparatus according to claim 1, wherein the plurality of performance levels differ in at least one of a clock frequency and voltage to be supplied to the processor.

### Claim 5

A load control method executed by a computer including a processor capable of switching a performance level to one of a plurality of performance levels with different power consumption, the load control method comprising:
detecting times when the performance level of the processor was increased from a first level to a second level, the first level being lower than a threshold, the second level being equal to or greater than the threshold;
calculating an average time period between the detected times; and
changing, according to the calculated average time period, a determination interval for determining whether to switch the performance level of the processor.

### Claim 6

A non-transitory computer-readable recording medium storing a load control program causing a computer including a processor capable of switching a performance level to one of a plurality of performance levels with different power consumption to perform a process comprising:
detecting times when the performance level of the processor was increased from a first level to a second level, the first level being lower than a threshold, the second level being equal to or greater than the threshold;
calculating an average time period between the detected times; and
changing, according to the calculated average time period, a determination interval for determining whether to switch the performance level of the processor.