# US 9,436,264 B2 · Saving power when in or transitioning to a static mode of a processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,264 B2 - Document ID: US9436264B2 - Status: Granted - Kind: B2 - Application number: 12/987,423 - Filed: 2011-01-10 - Published: 2011-05-05 - Granted: 2016-09-06 - Earliest claimed: 2000-10-23 - Assignees: Intellectual Ventures Holding 81 LLC - Applicants: Andrew Read; Sameer Halepete; Keith Klayman - Inventors: Andrew Read; Sameer Halepete; Keith Klayman - Web page: https://patentgrep.com/patent/US9436264B2 ## CPC - G06F 1/3296: by lowering the supply or operating voltage - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode - G06F 1/3237: by disabling clock generation or distribution - G06F 1/3287: by switching off individual functional units in the computer system - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled. ## Claims ### Claim 1 A method comprising: transitioning a processor to a reduced operation mode within a variable time allowed that varies based on a processor configuration; and reducing a voltage to the processor by a value dependent on the variable time allowed, wherein the voltage reduced by the value varies with a variation in the voltage and is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode. ### Claim 2 (depends on 1) The method of claim 1, wherein said transitioning comprises: disabling a clock of the processor. ### Claim 3 (depends on 1) The method of claim 1, wherein the voltage reduced by the value is sufficient to permit the processor to transition from the reduced operation mode to an operation mode within the variable time allowed. ### Claim 4 (depends on 1) The method of claim 1, wherein the reduced operation mode is a deep sleep mode. ### Claim 5 (depends on 1) The method of claim 1, wherein said transitioning comprises transitioning a voltage regulator from a first regulation mode to a second regulation mode, and wherein said reducing comprises generating the voltage by using the voltage regulator. ### Claim 6 (depends on 5) The method of claim 5, wherein the voltage regulator comprises a feedback circuit coupled to an output terminal of the voltage regulator. ### Claim 7 (depends on 1) The method of claim 1, wherein said transitioning comprises: responsive to a stop clock signal, transitioning the processor to the reduced operation mode. ### Claim 8 An apparatus comprising: a processor configured to operate in a reduced operation mode; and a circuit configured to reduce a voltage to the processor by a value dependent on a variable time allowed for the processor to transition to the reduced operation mode, wherein the voltage reduced by the value varies with a variation in the voltage and is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode, and wherein the variable time allowed varies based on a processor configuration. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein a clock of the processor is disabled in the reduced operation mode. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein the voltage reduced by the value is sufficient to permit the processor to transition from the reduced operation mode to an operation mode within the variable time allowed. ### Claim 11 (depends on 8) The apparatus of claim 8, wherein the reduced operation mode is a deep sleep mode. ### Claim 12 (depends on 8) The apparatus of claim 8, wherein the circuit comprises a voltage regulator, and wherein the voltage regulator comprises a feedback circuit coupled to an output terminal of the voltage regulator. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the voltage regulator is configured to operate in a first regulation mode and in a second regulation mode. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the voltage regulator generates the voltage while operating in the second regulation mode. ### Claim 15 (depends on 8) The apparatus of claim 8, wherein the processor operates in the reduced operation mode in response to a stop clock signal. ### Claim 16 A circuit comprising: an input terminal; an output terminal; and a voltage regulator coupled to the input and output terminals, wherein the voltage regulator is configured to reduce a voltage to a processor by a value dependent on a variable time allowed for the processor to transition to a reduced operation mode, wherein the voltage reduced by the value varies with a variation in the voltage and is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode, and wherein the variable time allowed varies based on a processor configuration. ### Claim 17 (depends on 16) The circuit of claim 16, wherein the voltage reduced by the value is sufficient to permit the processor to transition from the reduced operation mode to an operation mode within the variable time allowed. ### Claim 18 (depends on 16) The circuit of claim 16, wherein the voltage regulator is configured to operate in a first regulation mode and in a second regulation mode. ### Claim 19 (depends on 18) The circuit of claim 18, wherein the voltage regulator generates the voltage while operating in the second regulation mode. ### Claim 20 (depends on 16) The circuit of claim 16, wherein the reduced operation mode is a deep sleep mode. ### Claim 21 (depends on 16) The circuit of claim 16, wherein the voltage regulator includes a feedback circuit coupled to the output terminal.