# US 9,436,254 B2 · Method and apparatus for per core performance states > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,254 B2 - Document ID: US9436254B2 - Status: Granted - Kind: B2 - Application number: 13/976,682 - Filed: 2012-03-13 - Published: 2014-08-14 - Granted: 2016-09-06 - Earliest claimed: 2012-03-13 - Assignees: Intel Corporation - Applicants: Malini K. Bhandaru; Eric J. Dehaemer; Samuel W. Ho; Scott P. Bobholz; Chris Poirier - Inventors: Malini K. Bhandaru; Eric J. Dehaemer; Samuel W. Ho; Scott P. Bobholz; Chris Poirier - Web page: https://patentgrep.com/patent/US9436254B2 ## CPC - G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode - G06F 1/3243: {Power saving in microcontroller unit} - G06F 1/329: by task scheduling - G06F 9/5094: {where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - G06F 1/324: by lowering clock frequency - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/3296: by lowering the supply or operating voltage - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance. ## Claims ### Claim 1 A processor comprising: a plurality of cores, wherein each core comprises logic to: receive a performance state request from each of one or more threads; resolve the performance state request from each of the one or more threads to determine a resolved performance state request; and indicate the resolved performance state request to a power control module; and the power control module coupled to the plurality of cores, wherein the power control module is to facilitate each core to operate at a different performance state from the other cores based at least in part on the resolved performance state from each of the plurality of cores. ### Claim 2 (depends on 1) The processor of claim 1, wherein the power control module is to: facilitate each core to operate at a voltage level and a frequency setting that are different from the other cores. ### Claim 3 (depends on 1) The processor of claim 1, wherein the power control module is further to: determine the resolved performance state request from each core; send a multi-cast message to all cores having a common resolved performance state to switch to the common resolved performance state; and send an uni-cast message to each core having a different resolved performance state from the common resolved performance state to switch to the different resolved performance state. ### Claim 4 (depends on 1) The processor of claim 1, wherein each core comprises a register, and wherein the logic in each core is to set one or more bits of the register to indicate the resolved performance state request to the power control module. ### Claim 5 (depends on 1) The processor of claim 1, wherein the logic is to: determine a first maximum performance state of the one or more threads; determine a second maximum performance state from the performance state request from each of the one or more threads; determine whether the second maximum performance state is higher than the first maximum performance state; and determine the resolved performance state request based on the second maximum performance state in response to a determination that the second maximum performance state is different from the first maximum performance state. ### Claim 6 (depends on 1) The processor of claim 1, wherein the performance state request from each of one or more threads comprises a sleep state request, and wherein the logic is to: suppress the sleep state request from each of the one or more threads when a duration of the sleep state request is less than a duration of a core switch to the sleep state. ### Claim 7 (depends on 1) The processor of claim 1, wherein the performance state request from each of one or more threads comprises a transient sleep state request, and wherein the logic is to: retain a voting right for each thread having the transient sleep state request. ### Claim 8 (depends on 1) The processor of claim 1, wherein the performance state request from each of one or more threads comprises a wake request, and wherein the logic is to: determine a prior performance state of each thread having the wake request, wherein the prior performance state is a performance state of each thread prior to entry into a sleep state; and determine the resolved performance state request based on the prior performance state of each thread having the wake request. ### Claim 9 (depends on 1) The processor of claim 1, wherein the power control module is further to: determine that all resolved performance state requests from each core are sleep state requests; and indicate that the processor is in a sleep state. ### Claim 10 A system comprising: a memory; a processor coupled with the memory, the processor comprising: a plurality of cores, wherein each core comprises logic to: receive a performance state request from each of one or more threads; resolve the performance state request from each of the one or more threads to determine a resolved performance state request; and indicate the resolved performance state request to a power control module; and the power control module coupled to the plurality of cores, wherein the power control module is to facilitate each core to operate at an independent performance state based at least in part on the resolved performance state from each of the plurality of cores. ### Claim 11 (depends on 10) The system of claim 10, wherein the power control module is to: facilitate each core to operate at an independent voltage level and an independent frequency setting such that thermal and electrical constraints of the system are not violated. ### Claim 12 (depends on 10) The system of claim 10, wherein the power control module is further to: determine the resolved performance state request from each core; send a multi-cast message to all cores having a common resolved performance state to switch to the common resolved performance state; and send an uni-cast message to each core having a different resolved performance state from the common resolved performance state to switch to the different resolved performance state. ### Claim 13 (depends on 10) The system of claim 10, wherein each core comprises a register, and wherein the logic in each core is to set one or more bits of the register to indicate the resolved performance state request to the power control module. ### Claim 14 (depends on 10) The system of claim 10, wherein the logic in each core is to: determine a first maximum performance state of the one or more threads; determine a second maximum performance state from the performance state request from each of the one or more threads; determine whether the second maximum performance state is different than the first maximum performance state; and determine the resolved performance state request based on the second maximum performance state in response to a determination that the second maximum performance state is different from the first maximum performance state. ### Claim 15 (depends on 10) The system of claim 10, wherein the performance state request from each of one or more threads comprises a sleep state request, and wherein the logic is to: suppress the sleep state request from each of the one or more threads when a duration of the sleep state request is less than a duration of a core switch to the sleep state. ### Claim 16 (depends on 10) The system of claim 10, wherein the performance state request from each of one or more threads comprises a transient sleep state request, and wherein the logic is to: retain a voting right for each thread having the transient sleep state request. ### Claim 17 (depends on 10) The system of claim 10, wherein the performance state request from each of one or more threads comprises a wake request, and wherein the logic is to: determine a prior performance state of each thread having the wake request, wherein the prior performance state is a performance state of each thread prior to entering a sleep state; and determine the resolved performance state request based on the prior performance state of each thread having the wake request. ### Claim 18 (depends on 10) The system of claim 10, wherein the power control module is further to: determine that all resolved performance state requests from each core are sleep state requests; and indicate that the processor is in a sleep state. ### Claim 19 A method comprising: receiving, in a logic of a core of a multicore processor, a performance state request from each of one or more threads; resolving, in the logic, the performance state request from each of the one or more threads to determine a resolved performance state request; and indicating, from the core, the resolved performance state request to a performance control module of the multicore processor. ### Claim 20 (depends on 19) The method of claim 19, wherein indicating the resolved performance state request to the performance control module comprises setting one or more bits of a register to indicate the resolved performance state request to the performance control module. ### Claim 21 (depends on 19) The method of claim 19, wherein resolving the performance state request from each of the one or more threads to determine the resolved performance state request comprises: determining a first maximum performance state of the one or more threads; determining a second maximum performance state from the performance state request from each of the one or more threads; determining whether the second maximum performance state is higher than the first maximum performance state; and determining the resolved performance state request based on the second maximum performance state in response to a determination that the second maximum performance state is different from the first maximum performance state. ### Claim 22 (depends on 19) The method of claim 19, wherein the performance state request from each of one or more threads comprises a sleep state request, and wherein resolving the performance state request from each of the one or more threads to determine the resolved performance state request comprises: suppressing the sleep state request from each of the one or more threads when a duration of the sleep state request is less than a duration of switching the core to the sleep state. ### Claim 23 (depends on 19) The method of claim 19, wherein the performance state request from each of one or more threads comprises a transient sleep state request, and wherein resolving the performance state request from each of the one or more threads to determine the resolved performance state request comprises: retaining a voting right for each thread having the transient sleep state request. ### Claim 24 (depends on 19) The method of claim 19, wherein the performance state request from each of one or more threads comprises a wake request, and wherein resolving the performance state request from each of the one or more threads to determine the resolved performance state request comprises: determining a prior performance state of each thread having the wake request, wherein the prior performance state is a performance state of each thread prior to entering a sleep performance state; and determining the resolved performance state request based on the prior performance state of each thread having the wake request.