# US 9,436,253 B2 · Dynamic voltage frequency scaling method and apparatus

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- Number: US 9,436,253 B2
- Document ID: US9436253B2
- Status: Granted
- Kind: B2
- Application number: 13/957,982
- Filed: 2013-08-02
- Published: 2014-03-06
- Granted: 2016-09-06
- Earliest claimed: 2012-08-29
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hwang Sub Lee; Jong Lae Park
- Web page: https://patentgrep.com/patent/US9436253B2

## CPC

- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/324: by lowering clock frequency
- G06F 1/3296: by lowering the supply or operating voltage
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

System-on-a-chip (SOC) includes a dynamic voltage frequency scaling (DVFS) control unit; and a central processing unit (CPU) to operate the DVFS control unit. By using the DVFS control unit, a DVFS table may be selectively used according to any of various scenarios or modes of operation, thereby performing DVFS control.

## Claims

### Claim 1

A system-on chip (SOC) comprising:
a central processing unit (CPU) to operate a dynamic voltage frequency scaling (DVFS) control unit,
the DVFS control unit comprising:
a SOC load calculating unit to calculate a SOC load based on at least one element of the SOC;
a DVFS table selecting unit for determining a scenario of a CPU operation based on a result of analyzing a pattern of the SOC load or according to an external input, and determining a DVFS table suitable for the scenario; and
a DVFS calculating unit for determining a DVFS operation corresponding to the SOC load and a current operating frequency, based on the determined DVFS table among a plurality of DVFS tables,
wherein each of the plurality of DVFS tables is configured to comprise up-thresholds and down-thresholds corresponding to operating frequencies of the CPU, and
the up-thresholds and the down-thresholds are calculated based on a plurality of OFSL (Operating Frequency to SOC Load) ratio values corresponding to the ratio between each of the plurality of operating frequencies and the SOC load.

### Claim 2 (depends on 1)

The SOC of claim 1, wherein the DVFS control unit further comprises a DVFS table storing unit for storing the plurality of DVFS tables and providing the plurality of DVFS tables to the DVFS table selecting unit.

### Claim 3 (depends on 1)

The SOC of claim 1,
wherein in some of the plurality of DVFS tables, ratios between the operating frequencies and the up-thresholds vary according to the operating frequencies.

### Claim 4 (depends on 1)

The SOC of claim 1,
wherein in some of the plurality of DVFS tables, ratios between the operating frequencies and the down-thresholds vary according to the operating frequencies.

### Claim 5 (depends on 1)

The SOC of claim 1, wherein the external input comprises application execution information and a CPU control signal.

### Claim 6 (depends on 1)

The SOC of claim 1, wherein the DVFS table selecting unit determines a DVFS table suitable for the scenario by selecting at least one of the plurality of DVFS tables.

### Claim 7 (depends on 1)

The SOC of claim 1, wherein the DVFS operation comprises a first policy and a second policy,
wherein the first policy increases the operating frequency of the CPU and an operating voltage of the SOC, and
the second policy decreases the operating frequency of the CPU and the operating voltage of the SOC.

### Claim 8 (depends on 1)

The SOC of claim 1, further comprising:
a performance monitoring unit for measuring the memory usage of at least one of the elements of the SOC and transmitting information regarding the memory usage to the DVFS control unit; and
a clock management unit for changing an operating frequency of the CPU to perform the DVFS operation, under control of the DVFS control unit.

### Claim 9 (depends on 1)

An electronic system comprising
the SOC of claim 1; and
a power management integrated circuit for generating an operating voltage of the SOC and applying the operating voltage to the SOC so as to perform a dynamic voltage frequency scaling (DVFS) operation.

### Claim 10

A dynamic voltage frequency scaling (DVFS) controlling method comprising:
calculating a system-on chip (SOC) load on at least one of elements of a SOC;
determining a scenario of a central processing unit (CPU), based on analyzing a pattern of the SOC load or according to an external input;
determining whether a current DVFS table is to be replaced with another DVFS table depending on the scenario; and
determining a DVFS operation corresponding to the SOC load and an operating frequency of the CPU, based on the current DVFS table or a replaced DVFS table,
wherein each of the plurality of DVFS tables is configured to comprise up-thresholds and down-thresholds corresponding to operating frequencies of the CPU, and
the up-thresholds and the down-thresholds are calculated based on a plurality of OFSL (Operating Frequency to SOC Load) ratio values corresponding to the ratio between each of the plurality of operating frequencies and the SOC load.

### Claim 11 (depends on 10)

The DVFS controlling method of claim 10, if it is determined that the current DVFS table is to be replaced with another DVFS table, further comprising determining a DVFS table suitable for the scenario by selecting at least one of a plurality of DVFS tables.

### Claim 12 (depends on 11)

The DVFS controlling method of claim 11,
and in some of the plurality of DVFS tables, ratios between the operating frequencies and the up-thresholds vary according to the operating frequencies.

### Claim 13 (depends on 11)

The DVFS controlling method of claim 11,
wherein in some of the plurality of DVFS tables, ratios between the operating frequencies and the down-thresholds vary according to the operating frequencies.

### Claim 14 (depends on 10)

The DVFS controlling method of claim 10, wherein the external input comprises application execution information and a CPU control signal.

### Claim 15 (depends on 10)

The DVFS controlling method of claim 10, wherein the DVFS operation comprises a first policy and a second policy,
wherein the first policy instructs to increase an operating frequency of CPU and an operating voltage of the SOC, and
the second policy instructs to decrease the operating frequency of the CPU and the operating voltage of the SOC.

### Claim 16

A system on a chip (SOC), comprising:
a multi-core processor;
system elements; and
a dynamic voltage frequency scaling (DVFS) controller, the DVFS controller to allot greater or lesser power to the SOC depending upon the SOC's mode of operation and current operating frequency, wherein the DVFS controller is configured to determine the mode of operation by analyzing system activity and to allot greater or lesser power according to one of a plurality of DVFS tables selected on the basis of a load pattern or an external input, wherein the external input comprises application execution information and/or a CPU control signal and each of the plurality of DVFS tables is configured to comprise up-thresholds and down-thresholds corresponding to operating frequencies of the CPU, and
the up-thresholds and the down-thresholds are calculated based on a plurality of OFSL (Operating Frequency to SOC Load) ratio values corresponding to the ratio between each of the plurality of operating frequencies and the SOC load.

### Claim 17 (depends on 16)

The SOC of claim 16, wherein the DFVS controller is configured to allot greater or lesser power by adjusting an operating frequency.

### Claim 18 (depends on 16)

The SOC of claim 16, wherein the DVFS controller is configured to allot greater or lesser power by adjusting an operating voltage.

### Claim 19 (depends on 16)

The SOC of claim 16, wherein the DVFS controller is configured to allot greater or lesser power by adjusting an operating voltage and frequency for a plurality of the cores of the multicore processor.

### Claim 20 (depends on 16)

An electronic system including the SOC of claim 16.