# US 9,436,244 B2 · Adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications

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- Number: US 9,436,244 B2
- Document ID: US9436244B2
- Status: Granted
- Kind: B2
- Application number: 13/831,892
- Filed: 2013-03-15
- Published: 2014-09-18
- Granted: 2016-09-06
- Earliest claimed: 2013-03-15
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Yun He; Narender R. Nagulapally; Sanjib Sarkar; Ivan Herrera Mejia; Ruchira K. Liyanage
- Web page: https://patentgrep.com/patent/US9436244B2

## CPC

- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- G06F 1/3253: {Power saving in bus}
- G06F 11/0706: {the processing taking place on a specific hardware platform or in a specific software environment}
- G06F 11/0754: {by exceeding limits}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 1/00: Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00 (architectures of general purpose stored program computers G06F15/76)
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed.

## Claims

### Claim 1

An apparatus comprising:
first logic, coupled to a first agent, to detect a first bit pattern that indicates a speculative entry of a second agent into a low power consumption state and to cause freezing of one or more control loops; and
second logic to detect a second bit pattern that indicates exit from the low power consumption state by the second agent and to cause unfreezing of the one or more control loops, wherein the second logic is to cause unfreezing of all of the one or more control loops in response to detection of the second bit pattern and a determination that that the second agent has not entered the low power consumption state.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the one or more control loops are to comprise one or more of: a CDR (Clock Data Recovery) control loop, an AGC (Automatic Gain Control) control loop, a DFE (Decision Feedback Equalization) control loop, and a CTOC (Continuous Time Offset Cancellation) control loop.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the one or more control loops are to comprise a plurality of control loops and wherein the second logic is to cause unfreezing of a CDR control loop prior to an AGC control loop, a DFE control loop, and a CTOC control loop.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the one or more control loops are to comprise a plurality of control loops and wherein the second logic is to inject an artificial frequency offset into a CDR control loop to assist fast locking through slow responsive phase regions, prior to enabling an AGC control loop, a DFE control loop, and a CTOC control loop.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the one or more control loops are to comprise a plurality of control loops and wherein the second logic is to unfreeze an AGC control loop, a DFE control loop, and a CTOC control loop in response to expiration of a timer that indicates acquisition of a CDR control loop.

### Claim 6 (depends on 1)

The apparatus of claim 1, further comprising logic to determine whether the second agent has in fact entered the low power consumption state after freezing of the one or more control loops and in response to expiration of a timer.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the first agent and the second agent are to be coupled via a link and wherein the link comprises a Peripheral Component Interconnect Express (PCIe) link.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the first bit pattern is to comprise an EIOS (Electronic Idle Ordered Set) bit pattern.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the second bit pattern is to comprise an EIEOS (Electronic Idle Exit Ordered Set) bit pattern.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the first agent is to comprise a PCIe controller.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the second agent is to comprise an input/output device.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the first agent and the second agent are to be coupled via a link.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the link is to comprise a point-to-point coherent interconnect.

### Claim 14 (depends on 1)

The apparatus of claim 1, wherein the first agent is to comprise one or more of the logic to detect the first bit pattern and the logic to detect the second bit pattern.

### Claim 15 (depends on 1)

The apparatus of claim 1, wherein one or more of the first agent, the second agent, and memory are on a same integrated circuit chip.

### Claim 16 (depends on 1)

The apparatus of claim 1, wherein the first bit pattern is to comprise at least four symbols, wherein the at least four symbols are to comprise “com idle idle idle” or a first four EIOS (Electronic Idle Ordered Set) symbols.

### Claim 17 (depends on 1)

The apparatus of claim 1, wherein the one or more control loops are to comprise a plurality of control loops and wherein the second logic is to cause unfreezing of a CDR control loop prior to an AGC control loop, a DFE control loop, and a CTOC control loop in response to detection of the second bit pattern and a determination that the second agent has entered the low power consumption state.

### Claim 18

A method comprising:
detecting, at a first agent, a first bit pattern that indicates a speculative entry of a second agent into a low power consumption state and to cause freezing of one or more control loops; and
detecting a second bit pattern that indicates exit from the low power consumption state by the second agent and to cause unfreezing of the one or more control loops, wherein the second logic causes unfreezing of all of the one or more control loops in response to detection of the second bit pattern and a determination that that the second agent has not entered the low power consumption state.

### Claim 19 (depends on 18)

The method of claim 18, wherein the one or more control loops comprise one or more of: a CDR (Clock Data Recovery) control loop, an AGC (Automatic Gain Control) control loop, a DFE (Decision Feedback Equalization) control loop, and a CTOC (Continuous Time Offset Cancellation) control loop.

### Claim 20 (depends on 18)

The method of claim 18, wherein the one or more control loops comprise a plurality of control loops and wherein detecting the second bit pattern causes unfreezing of a CDR control loop prior to an AGC control loop, a DFE control loop, and a CTOC control loop.

### Claim 21 (depends on 18)

The method of claim 18, wherein the one or more control loops comprise a plurality of control loops and wherein detecting the second bit pattern causes injection of an artificial frequency offset into a CDR control loop to assist fast locking through slow responsive phase regions, prior to enabling an AGC control loop, a DFE control loop, and a CTOC control loop.

### Claim 22 (depends on 18)

The method of claim 18, wherein the one or more control loops comprise a plurality of control loops and wherein detecting the second bit pattern causes unfreezing of an AGC control loop, a DFE control loop, and a CTOC control loop in response to expiration of a timer that indicates acquisition of a CDR control loop.

### Claim 23

A system comprising:
a processor having a first agent and a second agent; and
first logic to detect a first bit pattern that indicates a speculative entry of the second agent into a low power consumption state and to cause freezing of one or more control loops; and
second logic to detect a second bit pattern that indicates exit from the low power consumption state by the second agent and to cause unfreezing of the one or more control loops, wherein the second logic is to cause unfreezing of all of the one or more control loops in response to detection of the second bit pattern and a determination that that the second agent has not entered the low power consumption state.

### Claim 24 (depends on 23)

The system of claim 23, wherein the one or more control loops are to comprise one or more of: a CDR (Clock Data Recovery) control loop, an AGC (Automatic Gain Control) control loop, a DFE (Decision Feedback Equalization) control loop, and a CTOC (Continuous Time Offset Cancellation) control loop.

### Claim 25 (depends on 23)

The system of claim 23, wherein the one or more control loops are to comprise a plurality of control loops and wherein the logic to detect the second bit pattern is to cause unfreezing of a CDR control loop prior to an AGC control loop, a DFE control loop, and a CTOC control loop.

### Claim 26 (depends on 23)

The system of claim 23, wherein the one or more control loops are to comprise a plurality of control loops and wherein the logic to detect the second bit pattern is to inject an artificial frequency offset into a CDR control loop to assist fast locking through slow responsive phase regions, prior to enabling an AGC control loop, a DFE control loop, and a CTOC control loop.

### Claim 27 (depends on 23)

The system of claim 23, wherein the one or more control loops are to comprise a plurality of control loops and wherein the logic to detect the second bit pattern is to unfreeze an AGC control loop, a DFE control loop, and a CTOC control loop in response to expiration of a timer that indicates acquisition of a CDR control loop.