Clock conversion apparatus with an elastic store memory from which data is written in synchronization with a first clock and read out in synchronization with a second clock
AssigneeFujitsu Limited
InventorsMakoto Shimizu, Masato Hori
Life of this patent
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Abstract
A clock conversion apparatus comprising, an elastic store memory in which data are written in synchronization with a first clock and from which data are read out in synchronization with a second clock, a phase comparator for detecting phase difference between a third clock obtained by imparting a first variable phase shift to a divided clock of the first clock and a fourth clock obtained by imparting a second variable phase shift to a divided clock of the second clock, and an oscillator for generating a clock having frequency in accordance with the phase difference as the second clock.
Claims8
A clock conversion apparatus comprising:
- an elastic store memory in which data are written in synchronization with a first clock and from which data are read out in synchronization with a second clock;
- a first phase shifter configured to generate a first plurality of different clocks by imparting a first variable phase shift to a divided clock of the first clock;
- a second phase shifter configured to generate a second plurality of different clocks by imparting a second variable phase shift to a divided clock of the second clock;
- a first selector configured to output a third clock from among the first plurality of different clocks generated by the first phase shifter by selecting the first variable phase shift in accordance with a number of times of stuff reception;
- a second selector configured to output a fourth clock from among the second plurality of different clocks generated by the second phase shifter by selecting the second variable phase shift in accordance with the number of times of stuff reception;
- a phase comparator configured to detect a phase difference between the third clock and the fourth clock;
- and
- an oscillator configured to generate the second clock having a frequency in accordance with the phase difference.
A frequency control method for controlling frequency of read-out clock of an elastic store memory into which data are written in synchronization with a first clock and from which data are read out in synchronization with a second clock, comprising:
- generating a first plurality of different clocks by imparting a first variable phase shift to a divided clock of the first clock;
- generating a second plurality of different clocks by imparting a second variable phase shift to a divided clock of the second clock;
- outputting a third clock from among the first plurality of different clocks by selecting the first variable phase shift in accordance with a number of times of stuff reception;
- outputting a fourth clock from among the second plurality of different clocks by selecting the second variable phase shift in accordance with a number of times of stuff reception;
- detecting a phase difference between the third clock and the fourth clock;
- and
- controlling the frequency of the second clock in accordance with the phase difference.
Dependencies are inferred from the claim text.