# US 9,436,210 B1 · Control—mechanism for selectively shorting clock grid by electrically connecting and disconnecting clock branches once per clock cycle > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,210 B1 - Document ID: US9436210B1 - Status: Granted - Kind: B1 - Application number: 14/093,587 - Filed: 2013-12-02 - Granted: 2016-09-06 - Earliest claimed: 2010-03-03 - Assignees: Marvell International Ltd. - Applicants: Marvell International Ltd. - Inventors: Kim Schuttenberg; Franco Ricci - Web page: https://patentgrep.com/patent/US9436210B1 ## CPC - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems, methods, and other embodiments are described that are associated with selective shorting of clock branches. In one embodiment, an apparatus includes a selective shorting device connected between a first clock branch that conducts a slow clock signal having a first frequency and a second clock branch that conducts a fast clock signal having a second frequency that is an integer multiple of the first frequency. The selective shorting device is configured to electrically connect and disconnect the first clock branch and the second clock branch. The selective shorting control mechanism is configured to control the selective shorting device to electrically connect the clock branches during a controlling portion of the slow clock signal. ## Claims ### Claim 1 An apparatus, comprising: a selective shorting device connected between a first clock branch that conducts a slow clock signal having a first frequency and a second clock branch that conducts a fast clock signal having a second frequency that is an integer multiple of the first frequency; wherein the selective shorting device is configured to electrically connect and disconnect the first clock branch and the second clock branch; and a selective shorting control mechanism configured to, once per slow clock cycle: control the selective shorting device to electrically connect the first clock branch to the second clock branch; and control the selective shorting device to electrically disconnect the first clock branch from the second clock branch. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein: the selective shorting device comprises a pass gate circuit that electrically connects the clock branches in response to a control signal from the selective shorting control mechanism; and the selective shorting control mechanism comprises an electrically conductive path between the first clock branch and the pass gate circuit. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein: the selective shorting device comprises a pass gate circuit that electrically connects the clock branches in response to a control signal from the selective shorting control mechanism; and the selective shorting control mechanism comprises a pass gate circuit enabling pulse generated by the controlling portion of the second clock signal. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first clock branch is in a first power domain and the second clock branch is in a second power domain. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein: the selective shorting device comprises a pass gate circuit that electrically connects the clock branches in response to a control signal from the selective shorting control mechanism; and the selective shorting control mechanism comprises a pass gate circuit enabling pulse generated by a clock signal circuit that generates the slow clock signal. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the first clock branch and the second clock branch comprise a plurality of buffers and the selective shorting device is located between a path of buffers in the first clock branch and a path of buffers in the second clock branch. ### Claim 7 A method, comprising: sensing a controlling portion of a slow clock signal having a first frequency conducted by a first clock branch; and once per slow clock cycle: electrically connecting the first clock branch to a second clock branch during the sensed controlling portion of the slow clock signal, and electrically disconnecting the first clock branch from the second clock branch, wherein the second clock branch conducts a fast clock signal having a second frequency that is an integer multiple of the slow clock signal. ### Claim 8 (depends on 7) The method of claim 7, wherein the electrically connecting is performed by a pass gate circuit that electrically connects the first clock branch to the second clock branch in response to a control signal provided by an electrically conductive path between the first clock branch and the pass gate circuit. ### Claim 9 (depends on 7) The method of claim 7, wherein the electrically connecting is performed by a pass gate circuit that electrically connects the first clock branch to the second clock branch in response to a pass gate circuit enabling pulse generated by a clock signal generator that generates the slow clock signal. ### Claim 10 (depends on 7) The method of claim 7, wherein the first clock branch is in a first power domain and the second clock branch is in a second power domain. ### Claim 11 (depends on 7) The method of claim 7, wherein electrically connecting the first clock branch to the second clock branch comprises electrically connecting the clock branches based, at least in part, on a relative state of the fast clock signal and the slow clock signal. ### Claim 12 (depends on 7) The method of claim 7, wherein electrically connecting the first clock branch and the second clock branch comprises connecting a first path of buffers in the first clock branch to a second path of buffers in the second clock branch. ### Claim 13 A device comprising: a clock tree comprising a first clock branch that conducts a slow clock signal at a first frequency and a second clock branch that conducts a fast clock signal at a second frequency that is an integer multiple of the first frequency; a selective shorting device electrically coupled between the first clock branch and second clock branch, the selective shorting device being configured to selectively electrically connect the first clock branch to the second clock branch, and to selectively electrically disconnect the first clock branch from the second clock branch; and a selective shorting control mechanism configured to, once per slow clock cycle: control the selective shorting device to electrically connect the first clock branch to the second clock branch; and control the selective shorting device to electrically disconnect the first clock branch from the second clock branch. ### Claim 14 (depends on 13) The device of claim 13, wherein: the selective shorting device comprises a pass gate circuit that electrically connects the first clock branch to the second clock branch in response to a rising edge of a control signal from the selective shorting control mechanism; and the selective shorting control mechanism comprises an electrically conductive path between the first clock branch and the pass gate circuit. ### Claim 15 (depends on 13) The device of claim 13, wherein: the selective shorting device comprises a pass gate circuit that electrically connects the first clock branch to the second clock branch in response to a rising edge of a control signal from the selective shorting control mechanism; and the selective shorting control mechanism comprises a pass gate circuit enabling pulse generated by a clock signal generator that generates the slow clock signal. ### Claim 16 (depends on 13) The device of claim 13, wherein the first clock branch and the second clock branch comprise a plurality of buffers and the selective shorting device is located between a first path of buffers in the first clock branch and a second path of buffers in the second clock branch. ### Claim 17 (depends on 13) The device of claim 13, wherein the first clock branch is in a first power domain and the second clock branch is in a second power domain.