# US 9,436,206 B2 · Temperature and process compensated current reference circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,206 B2 - Document ID: US9436206B2 - Status: Granted - Kind: B2 - Application number: 14/519,225 - Filed: 2014-10-21 - Published: 2015-07-02 - Granted: 2016-09-06 - Earliest claimed: 2014-01-02 - Assignees: STMicroelectronics (Shenzhen) R&D Co. Ltd - Applicants: STMicroelectronics (Shenzhen) R&D Co. Ltd - Inventors: Yong Feng Liu - Web page: https://patentgrep.com/patent/US9436206B2 ## CPC - G05F 3/267: {using both bipolar and field-effect technology} - G05F 1/463: {Sources providing an output which depends on temperature} - G05F 3/242: {with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage} - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract A reference current path carries a reference current. A first transistor is coupled to the reference current path. A second transistor is also coupled to the reference current path. The first and second transistors are connected in parallel to carry the reference current. The first transistor is biased by a first voltage (which is a bandgap voltage plus a threshold voltage). The second transistor is biased by a second voltage (which is a PTAT voltage plus a threshold voltage). The first and second transistors are thus biased by voltages having different and opposite temperature coefficients with a result that the temperature coefficients of the currents flowing in the first and second transistors are opposite and the reference current accordingly has a low temperature coefficient. ## Claims ### Claim 1 A circuit, comprising: a reference current path configured to carry a reference current; a first transistor coupled to the reference current path and configured to carry at first portion of the reference current, said first transistor having a control terminal configured to be biased by a first voltage derived from a bandgap voltage; and a second transistor coupled to the reference current path and configured to carry a second portion of the reference current, said second transistor having a control terminal configured to be biased by a second voltage derived from a proportional to absolute temperature (PTAT) voltage; wherein the first and second transistors are coupled in parallel with each other; and wherein a temperature coefficient of the current flowing in the first transistor and a temperature coefficient of the current flowing in the second transistor are opposite. ### Claim 2 (depends on 1) The circuit of claim 1, further comprising a bandgap reference voltage generator circuit configured to generate the bandgap voltage. ### Claim 3 (depends on 1) The circuit of claim 1, further comprising a bandgap reference voltage generator circuit configured to generate a first current and including a circuit configured to generate the first voltage by passing the first current across a diode-connected transistor. ### Claim 4 (depends on 3) The circuit of claim 3, further including a mirror circuit configured to generate a second current mirrored from the first current, and an additional circuit configured to generate the second voltage by passing the second current across a resistor. ### Claim 5 (depends on 4) The circuit of claim 4, wherein the additional circuit is further configured to generate the second voltage by passing the second current across a diode connected transistor coupled in series with the resistor. ### Claim 6 (depends on 5) The circuit of claim 5, wherein the diode connected transistor has a control terminal coupled to the control terminal of the second transistor. ### Claim 7 (depends on 1) The circuit of claim 1, further including: an operational amplifier having a first input configured to receive a reference voltage and a second input coupled to the parallel coupled first and second transistors; and a third transistor having a control terminal coupled to an output of the operational amplifier, the third transistor defining the reference current path and coupled in series with the parallel coupled first and second transistors. ### Claim 8 (depends on 7) The circuit of claim 7, wherein the operational amplifier is configured to supply an additional current to the second input of the operational amplifier, the circuit further including a current source configured to generate an offset current applied to the second input of the operational amplifier, the offset current being substantially equal to the additional current. ### Claim 9 (depends on 8) The circuit of claim 8, further including a current mirror circuit including said current source, the current mirror circuit configured to mirror a current derived from the first voltage to generate said offset current. ### Claim 10 A circuit, comprising: an output transistor configured to carry a reference current; a first transistor coupled in series with the output transistor to carry a first portion of the reference current; a second transistor coupled in series with the output transistor to carry a second portion of the reference current; wherein the first and second transistors are coupled in parallel to each other; a bandgap reference voltage generator circuit configured to generate a bandgap reference voltage; a first biasing circuit configured to generate a first biasing voltage for application to a control terminal of the first transistor, said first biasing voltage derived from said bandgap reference voltage; and a second biasing circuit configured to generate a second biasing voltage for application to a control terminal of the second transistor, said second biasing voltage generated from a proportional to absolute temperature (PTAT) current mirrored from a current flowing in the bandgap reference voltage generator circuit; wherein a temperature coefficient of the current flowing in the first transistor and a temperature coefficient of the current flowing in the second transistor are opposite. ### Claim 11 (depends on 10) The circuit of claim 10, further comprising: an operational amplifier having a first input configured to receive a reference voltage and a second input coupled to the parallel coupled first and second transistors; and wherein the output transistor has a control terminal coupled to an output of the operational amplifier. ### Claim 12 (depends on 10) The circuit of claim 10, wherein the first biasing circuit is configured to generate the first biasing voltage by passing a current within the bandgap reference voltage generated circuit across a diode-connected transistor. ### Claim 13 (depends on 10) The circuit of claim 10, wherein the second biasing circuit is configured to generate the second biasing voltage by passing the PTAT current across a resistor. ### Claim 14 (depends on 13) The circuit of claim 13, wherein the second biasing circuit is further configured to generate the second biasing voltage by passing the PTAT current across a diode connected transistor coupled in series with the resistor. ### Claim 15 (depends on 11) The circuit of claim 11, wherein the operational amplifier is further configured to supply an additional current to the second input of the operational amplifier, the circuit further including a current source configured to generate an offset current applied to the second input of the operational amplifier, the offset current being substantially equal to the additional current. ### Claim 16 (depends on 15) The circuit of claim 15, further including a current mirror circuit including said current source, the current mirror circuit configured to mirror the second current to generate said offset current. ### Claim 17 A circuit, comprising: a reference current path configured to carry a reference current; a first transistor coupled in series with the reference current path to carry the reference current; a second transistor coupled in series with the first transistor to the reference current; a bandgap reference voltage generator circuit configured to generate a bandgap reference voltage; a first biasing circuit configured to generate a first biasing voltage for application to a control terminal of the first transistor, said first biasing voltage derived from said bandgap reference voltage; and a second biasing circuit configured to generate a second biasing voltage for application to a control terminal of the second transistor, said second biasing voltage generated from a proportional to absolute temperature (PTAT) current mirrored from a current flowing in the bandgap reference voltage generator circuit. ### Claim 18 (depends on 17) The circuit of claim 17, wherein the first biasing circuit is configured to generate the first biasing voltage in excess of the bandgap reference voltage. ### Claim 19 (depends on 17) The circuit of claim 17, wherein the first biasing circuit is configured to generate the first biasing voltage by passing the current flowing in the bandgap reference voltage generator circuit across a diode-connected transistor. ### Claim 20 (depends on 17) The circuit of claim 17, wherein the second biasing voltage is developed by passing the proportional to absolute temperature (PTAT) current across a resistor. ### Claim 21 (depends on 20) The circuit of claim 20, wherein the second voltage is further developed by passing the PTAT current across a diode connected transistor coupled in series with the resistor. ### Claim 22 (depends on 21) The circuit of claim 21, wherein the diode connected transistor has a control terminal coupled to the control terminal of the second transistor.