# US 9,436,196 B2 · Voltage regulator and method

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- Number: US 9,436,196 B2
- Document ID: US9436196B2
- Status: Granted
- Kind: B2
- Application number: 14/464,214
- Filed: 2014-08-20
- Published: 2016-02-25
- Granted: 2016-09-06
- Earliest claimed: 2014-08-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hao-Chieh Chan
- Web page: https://patentgrep.com/patent/US9436196B2

## CPC

- G05F 1/56: using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence)
- G05F 1/613: using semiconductor devices in parallel with the load as final control devices (G05F1/461 takes precedence)
- G05F 1/618: using semiconductor devices in series and in parallel with the load as final control devices (G05F1/461 takes precedence)
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES

## Abstract

A device includes a voltage buffer, a load compensation circuit, and a closed-loop current feedback circuit. The voltage buffer is configured to output an output voltage and an output current. The output current is the sum of a load current and a bias current. The load compensation circuit is configured to output the bias current at a variable level based on a variation in the load current. The closed-loop current feedback circuit is configured to feedback a voltage level based on the variation to the load compensation circuit.

## Claims

### Claim 1

A device comprising:
a voltage buffer comprising first and second transistors and being configured to output an output voltage and an output current, the output current being a sum of a load current and a bias current;
a load compensation circuit configured to output the bias current at a variable level based on a variation in the load current; and
a closed-loop current feedback circuit comprising a current mirror including a third transistor and a fourth transistor and configured to mirror the output current, the closed-loop current feedback circuit configured to feedback a voltage level based on the variation to the load compensation circuit,
wherein the first transistor of the voltage buffer comprises a drain electrode coupled with a gate electrode of the first transistor.

### Claim 2 (depends on 1)

The device of claim 1, wherein the load compensation circuit comprises:
a reference current source configured to provide a reference current proportional to the output current;
a feedback current source configured to mirror the output current including the variation;
a current mirror configured to feedback a first current proportional to the load current;
a current source configured to output a second current equal to a difference between the reference current and the first current; and
a bias current source configured to output the bias current proportional to the second current by mirroring the second current.

### Claim 3 (depends on 1)

The device of claim 1, wherein the voltage buffer comprises:
the first transistor comprising:
a source electrode coupled with a reference voltage node; and
the second transistor comprising:
a source electrode coupled with the load compensation circuit; and
a gate electrode coupled with the gate electrode of the first transistor.

### Claim 4 (depends on 3)

The device of claim 3, wherein the closed-loop current feedback circuit comprises:
the third transistor comprising:
a drain electrode coupled with a drain electrode of the second transistor; and
a gate electrode electrically coupled with the drain electrode of the third transistor; and
the fourth transistor comprising:
a drain electrode coupled with the gate electrode of the first transistor; and
a gate electrode coupled with the gate electrode of the third transistor.

### Claim 5 (depends on 1)

The device of claim 1, further comprising:
a resistive divider configured to output a reference voltage equal to the output voltage; and
an amplifier circuit configured to output a voltage equal to the reference voltage to the voltage buffer.

### Claim 6 (depends on 5)

The device of claim 5, wherein the amplifier circuit is electrically connected as a unity gain buffer.

### Claim 7

A device comprising:
a resistive divider configured to output a reference voltage;
an amplifier circuit configured to output a first voltage equal to the reference voltage;
a voltage buffer comprising first and second transistors and being configured to output an output voltage equal to the first voltage;
a closed-loop current feedback circuit comprising a current mirror including a third and a fourth transistor and configured to output a second voltage based on an output current of the voltage buffer; and
a load current compensation circuit configured to vary the output current and a second current of the voltage buffer based on the second voltage,
wherein the first transistor of the voltage buffer comprises a drain electrode coupled with a gate electrode of the first transistor.

### Claim 8 (depends on 7)

The device of claim 7, wherein
the voltage buffer comprises:
the first transistor comprising:
a source electrode coupled with an output terminal of the amplifier circuit; and
the second transistor comprising:
a source electrode coupled with the load compensation circuit; and
a gate electrode electrically coupled with the gate electrode of the first transistor; and
the load current compensation circuit comprises:
a current mirror configured to output the second current to the first transistor based on the second voltage.

### Claim 9 (depends on 8)

The device of claim 8, wherein the closed-loop current feedback circuit comprises:
the third transistor comprising
a drain electrode coupled with a drain electrode of the second transistor; and
a gate electrode coupled with the drain electrode of the third transistor; and
the fourth transistor having:
a drain electrode coupled with the gate electrode of the first transistor; and
a gate electrode coupled with the gate electrode of the third transistor.

### Claim 10 (depends on 7)

The device of claim 7, wherein the load compensation circuit comprises:
a reference current source configured to provide a reference current proportional to the output current;
a transistor configured to mirror the output current;
a first current source configured to draw a first current from the reference current source, the first current being proportional to a load current component of the output current;
a second current source configured to draw a second current from the reference current source, the second current being equal to a difference between the reference current and the first current;
a third current source configured to draw a third current from the transistor, the third current being proportional to the load current component;
a fourth current source configured to draw a fourth current from the transistor, the fourth current being mirrored from the second current source; and
a bias current source configured to vary the output current by outputting the bias current by mirroring the second current.

### Claim 11 (depends on 10)

The device of claim 10, wherein the load compensation circuit further comprises:
a second transistor configured to mirror the output current;
a fifth current source configured to draw a fifth current from the second transistor, the fifth current being proportional to the output current; and
a sixth current source configured to mirror the fifth current to draw a sixth current at an output node of the amplifier circuit.

### Claim 12 (depends on 7)

The device of claim 7, further comprising:
a bias circuit configured to supply a first bias current to the resistive divider, and to supply a second bias current to the amplifier circuit.

### Claim 13

A method comprising:
outputting an output voltage at a predetermined value using a voltage buffer of a voltage regulator, the voltage buffer comprising first and second transistors, the first transistor having a drain electrode coupled with a gate electrode of the first transistor;
sensing a change in output current of the voltage buffer using a current mirror of a closed-loop current feedback circuit to mirror the output current; the current mirror including at least two transistor different from the first and the second transistors of the voltage buffer; and
restoring the output current to a target value by changing a bias current of a variable current source in response to the change in the output current.

### Claim 14 (depends on 13)

The method of claim 13, wherein restoring the output current further comprises:
mirroring the output current using a third transistor to generate a first mirrored current;
drawing a first current proportional to the bias current from the third transistor;
drawing a second current as a difference between the first mirrored current and the first current;
generating a reference current by a reference current source;
drawing a third current equal to the second current from the reference current source;
drawing a fourth current as a difference between the reference current and the third current; and
changing the bias current by mirroring the fourth current.

### Claim 15 (depends on 14)

The method of claim 14, further comprising:
mirroring the output current using a fourth transistor to generate a second mirrored current;
drawing a fifth current from the fourth transistor equal to the second mirrored current; and
varying input voltage of the voltage buffer by mirroring the fifth current to an input terminal of the voltage buffer.

### Claim 16 (depends on 13)

The method of claim 13, wherein sensing the change further comprises:
sensing a change in load current drawn from the voltage buffer using a load circuit coupled with the voltage buffer.

### Claim 17 (depends on 13)

The method of claim 13, further comprising:
generating a reference voltage using a bias circuit and a resistive divider; and
outputting a first voltage to the voltage buffer using an amplifier circuit based on the reference voltage.

### Claim 18 (depends on 17)

The method of claim 17, wherein outputting the first voltage further comprises:
buffering the first voltage using a unity gain buffer including the amplifier circuit.

### Claim 19 (depends on 13)

The method of claim 13, wherein sensing the change further comprises:
conducting the output current through a third transistor; and
outputting a first voltage at a gate electrode of the third transistor based on a magnitude of the output current.

### Claim 20 (depends on 19)

The method of claim 19, wherein restoring the output current further comprises:
restoring the output current to the target value by changing the bias current of the variable current source based on the first voltage.