# US 9,436,092 B2 · Semiconductor fabrication utilizing grating and trim masks > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,436,092 B2 - Document ID: US9436092B2 - Status: Granted - Kind: B2 - Application number: 13/712,005 - Filed: 2012-12-12 - Published: 2013-10-03 - Granted: 2016-09-06 - Earliest claimed: 2012-03-30 - Assignees: Newport Fab, LLC - Applicants: Newport Fab, LLC - Inventors: George Talor; Edward Preisler; David J. Howard - Web page: https://patentgrep.com/patent/US9436092B2 ## CPC - G03F 7/203: {comprising an imagewise exposure to electromagnetic radiation or corpuscular radiation} - G03F 1/30: Alternating PSM, e.g. Levenson-Shibuya PSM; Preparation thereof - G03F 7/2022: {Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure} - G03F 7/70283: {Mask effects on the imaging process} - H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies - H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects} - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed are a method for fabricating a semiconductor device and the associated semiconductor structure. The method includes exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in the photoresist layer. The method further includes exposing the photoresist layer utilizing a trim mask having a blocking portion situated over a selected one of the unexposed lines. The photoresist layer may be developed after exposing the photoresist layer utilizing the trim mask. A line may then be etched into the semiconductor wafer where the selected one of the unexposed lines was blocked by the blocking portion of the trim mask. The width of the unexposed lines may be controlled by adjusting an exposure time or an exposure power for the photoresist layer while utilizing the grating mask. ## Claims ### Claim 1 A method for fabricating a semiconductor device, said method comprising: exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in said photoresist layer; exposing said photoresist layer utilizing a trim mask having a chrome line in a blocking portion situated over a selected one of said unexposed lines, wherein said trim mask includes at least two recesses having different depths adjacent to said chrome line, and wherein said chrome line is aligned with respective sidewalls of said at least two recesses. ### Claim 2 (depends on 1) The method of claim 1, further comprising developing said photoresist layer after said exposing said photoresist layer utilizing said trim mask. ### Claim 3 (depends on 1) The method of claim 1, further comprising controlling a width of said unexposed lines by adjusting an exposure time of said photoresist layer while utilizing said grating mask. ### Claim 4 (depends on 1) The method of claim 1, further comprising controlling a width of said unexposed lines by adjusting an exposure power for said photoresist layer while utilizing said grating mask. ### Claim 5 (depends on 1) The method of claim 1, wherein said photoresist layer comprises a positive photoresist. ### Claim 6 (depends on 5) The method of claim 5, further comprising etching a line into said semiconductor wafer where said selected one of said unexposed lines was blocked by said blocking portion of said trim mask. ### Claim 7 (depends on 1) The method of claim 1, wherein said photoresist layer comprises a negative photoresist. ### Claim 8 (depends on 1) The method of claim 1, wherein said grating mask comprises an alternating phase shift mask. ### Claim 9 (depends on 1) The method of claim 1, wherein said grating mask comprises an alternating phase shift mask, said alternating phase shift mask comprising: a chrome line to function as one of said plurality of grating lines; a first recess having a first depth and situated adjacent to said chrome line; a second recess having a second depth and situated adjacent to said chrome line on a side opposite of said first recess. ### Claim 10 (depends on 9) The method of claim 9, wherein radiation passing through said first recess is approximately 180 degrees out of phase with radiation passing through said second recess. ### Claim 11 A semiconductor wafer fabricated by a method comprising: exposing a photoresist layer disposed on said semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in said photoresist layer; exposing said photoresist layer utilizing a trim mask having a chrome line in a blocking portion situated over a selected one of said unexposed lines, wherein said trim mask includes at least two recesses having different depths adjacent to said chrome line, and wherein said chrome line is aligned with respective sidewalls of said at least two recesses. ### Claim 12 (depends on 11) The semiconductor wafer of claim 11, wherein said photoresist layer is developed after said exposing said photoresist layer utilizing said trim mask. ### Claim 13 (depends on 11) The semiconductor wafer of claim 11, wherein a width of said unexposed lines is controlled by adjusting an exposure time of said photoresist layer while utilizing said grating mask. ### Claim 14 (depends on 11) The semiconductor wafer of claim 11, wherein a width of said unexposed lines is controlled by adjusting an exposure power for said photoresist layer while utilizing said grating mask. ### Claim 15 (depends on 11) The semiconductor wafer of claim 11, wherein said photoresist layer comprises a positive photoresist. ### Claim 16 (depends on 15) The semiconductor wafer of claim 15, wherein a line is etched into said semiconductor wafer where said selected one of said unexposed lines was blocked by said blocking portion of said trim mask. ### Claim 17 (depends on 11) The semiconductor wafer of claim 11, wherein said photoresist layer comprises a negative photoresist. ### Claim 18 (depends on 11) The semiconductor wafer of claim 11, wherein said grating mask comprises an alternating phase shift mask. ### Claim 19 (depends on 11) The semiconductor wafer of claim 11, wherein said grating mask comprises an alternating phase shift mask, said alternating phase shift mask comprising: a chrome line to function as one of said plurality of grating lines; a first recess having a first depth and situated adjacent to said chrome line; a second recess having a second depth and situated adjacent to said chrome line on a side opposite of said first recess. ### Claim 20 (depends on 19) The semiconductor wafer of claim 19, wherein radiation passing through said first recess is approximately 180 degrees out of phase with radiation passing through said second recess.