# US 9,435,947 B2 · Integration of optical components in integrated circuits by separating two substrates with an insulation layer

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- Number: US 9,435,947 B2
- Document ID: US9435947B2
- Status: Granted
- Kind: B2
- Application number: 14/850,381
- Filed: 2015-09-10
- Published: 2015-12-31
- Granted: 2016-09-06
- Earliest claimed: 2013-06-25
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Errol T. Ryan
- Web page: https://patentgrep.com/patent/US9435947B2

## CPC

- G02B 6/12004: {Combinations of two or more optical elements}
- G02B 6/122: Basic optical elements, e.g. light-guiding paths
- G02B 6/43: Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
- G02F 1/025: in an optical waveguide structure (G02F1/017, {G02F1/2257} take precedence)
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 88/101: {comprising components on opposite major surfaces of semiconductor substrates}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/43: Layouts of interconnections
- H10W 20/4421: {the principal metal being copper}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/259: {Ceramics or glasses (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)}
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methodologies enabling integration of optical components in ICs and a resulting device are disclosed. Embodiments include: providing a first substrate layer of an IC separated from a second substrate level by an insulator layer; providing a transistor on the second substrate layer; and providing an optical component on the first substrate layer, the optical component being connected to the transistor.

## Claims

### Claim 1

An apparatus comprising:
a first substrate layer of an integrated circuit (IC), the first substrate layer including an optical component;
an insulator layer on the first substrate layer;
a second substrate layer separated, at least in part, from the first substrate layer by the insulator layer;
a transistor on the second substrate layer, the transistor being connected to the optical component
a waveguide on the first substrate layer, the waveguide being connected to the transistor; and
a heat transfer via (HTV) extending vertically through a horizontal portion of the insulator layer and the first substrate layer, the HTV being adjacent to the second substrate layer and aligned vertically with the transistor,
wherein the thickness of the insulator layer is greater than a thickness of the first substrate layer.

### Claim 2 (depends on 1)

The apparatus according to claim 1, further comprising:
the HTV being vertically aligned with the transistor, wherein the first and second substrate layers and the insulator layer extend horizontally.

### Claim 3 (depends on 1)

The apparatus according to claim 1, further comprising:
the first substrate layer being a silicon on insulator (SOI) layer of a wafer for the IC;
the insulator layer being a buried oxide (BOX) layer of the wafer;
the second substrate layer being a bulk silicon layer of the wafer; and
the HTV comprising aluminum nitride (AlN).

### Claim 4 (depends on 1)

The apparatus according to claim 1, comprising:
a through silicon via (TSV) through the insulator layer and the second substrate layer, the TSV connecting the transistor and optical component.

### Claim 5 (depends on 1)

The apparatus according to claim 1, further comprising:
the second substrate layer having a thickness greater than the thickness of the insulator layer.

### Claim 6 (depends on 1)

The apparatus according to claim 1, further comprising:
the first substrate layer having a thickness equal to a height of the optical component.

### Claim 7

An apparatus comprising:
a wafer for an integrated circuit (IC) comprising:
a bulk silicon layer extending in a horizontal direction;
a buried oxide (BOX) layer extending in the horizontal direction and having a thickness less than a thickness of the bulk silicon layer; and
a silicon on insulator (SOI) layer separated, at least in part, from the bulk silicon layer by the BOX layer, the SOI layer extending in the horizontal direction and having a thickness less than the thickness of the BOX layer;
at least one transistor on the bulk silicon layer;
an optical component in the SOI layer;
a through silicon via (TSV) extending vertically through the bulk silicon layer and the BOX layer, the TSV connecting the at least one transistor and the optical component; and
a heat transfer via (HTV) extending vertically through a horizontal portion of the BOX layer and the SOI layer, the HTV being adjacent to the bulk silicon layer and aligned vertically with the at least one transistor.

### Claim 8 (depends on 7)

The apparatus according to claim 7, wherein the SOI layer has a thickness equal to a height of the optical component.

### Claim 9

An apparatus comprising:
a first substrate layer of an integrated circuit (IC) separated from a second substrate layer by an insulator layer;
a transistor on the second substrate layer, the transistor being in direct contact with the second substrate layer;
a waveguide on the first substrate layer, the waveguide being connected to the transistor; and
a heat transfer via (HTV) extending vertically through a horizontal portion of the insulator layer and the first substrate layer, the HTV being adjacent to the second substrate layer and aligned vertically with the transistor,
wherein the thickness of the insulator layer is greater than a thickness of the first substrate layer.

### Claim 10 (depends on 9)

The apparatus according to claim 9, wherein
the first substrate layer is a silicon on insulator (SOI) layer of a wafer for the IC;
the insulator layer is a buried oxide (BOX) layer of the wafer;
the second substrate layer is a bulk silicon layer of the wafer; and
the HTV comprises aluminum nitride (AlN).

### Claim 11 (depends on 9)

The apparatus according to claim 9, comprising:
a through silicon via (TSV) through the insulator layer and the second substrate layer, the TSV connecting the transistor and waveguide.

### Claim 12 (depends on 9)

The apparatus according to claim 9, wherein:
the second substrate layer has a thickness greater than the thickness of the insulator layer; and
the first substrate layer has a thickness equal to a height of the waveguide.

### Claim 13 (depends on 9)

The apparatus according to claim 9, wherein:
the first and second substrate layers and the insulator layer comprise a wafer; and
the wafer is rotated, wherein the transistor is provided prior to rotating the wafer and the waveguide is provided after rotating the wafer or the waveguide is provided prior to rotating the wafer and the transistor is provided after the rotating the wafer.

### Claim 14 (depends on 10)

The apparatus according to claim 10, further comprising:
metal routes located on top of the bulk silicon layer.

### Claim 15 (depends on 14)

The apparatus according to claim 14, further comprising:
an inter-layer dielectric between the transistor and the metal routes.

### Claim 16 (depends on 14)

The apparatus according to claim 14, wherein the metal routes comprise copper.

### Claim 17 (depends on 10)

The apparatus according to claim 10, wherein the SOI layer comprises a plurality of recesses.

### Claim 18 (depends on 17)

The apparatus according to claim 17, further comprising a through silicon via (TSV) in each of the recesses.

### Claim 19 (depends on 18)

The apparatus according to claim 18, wherein each of the TSVs passes through the BOX layer.

### Claim 20 (depends on 19)

The apparatus according to claim 19, wherein each of the TSVs passes through the bulk silicon layer.