# US 9,435,863 B2 · Integrated circuit testing interface on automatic test equipment > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 9,435,863 B2 - Document ID: US9435863B2 - Status: Granted - Kind: B2 - Application number: 14/492,067 - Filed: 2014-09-21 - Published: 2015-07-30 - Granted: 2016-09-06 - Earliest claimed: 2014-01-24 - Assignees: Sitronix Technology Corp. - Applicants: Sitronix Technology Corp. - Inventors: Chun-Chi Chen; Hung-Wei Lai; Tsung-Jun Lee - Web page: https://patentgrep.com/patent/US9435863B2 ## CPC - G01R 31/31908: {Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns} - G01R 31/31905: {Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract An integrated circuit (IC) testing interface capable of upgrading an automatic test equipment (ATE) for testing a semiconductor device includes at least one pin for receiving or transmitting at least a test signal to a tester of the automatic test equipment, a plurality of digitizers coupled to the at least one pin for generating a digital signal, a processing means coupled to the plurality of digitizers for processing the digital signal, and a connection unit for connecting the processing means with a computing device for transmitting an output signal from the processing means to the computing device, where the IC testing interface is disposed between the tester and a prober of the automatic test equipment. ## Claims ### Claim 1 An integrated circuit (IC) testing interface, capable of upgrading an automatic test equipment (ATE) for testing a semiconductor device, the IC testing interface comprising: at least one pin, configured for receiving or transmitting at least one test signal to a tester of the automatic test equipment; a plurality of digitizers, coupled to the at least one pin for generating a digital signal; a processing means, coupled to the plurality of digitizers for processing the digital signal; and a connection unit, configured for connecting the processing means with a computing device for transmitting an output signal from the processing means to the computing device; wherein the IC testing interface is disposed between the tester and a prober of the automatic test equipment; wherein the at least one pin comprises: a first pin, configured for transmitting a first test signal of the at least one test signal to the tester of the ATE, wherein the first test signal comprises an enabling signal for reading or writing a testing datum; a second pin, configured for transmitting a second test signal of the at least one test signal to the tester of the ATE, wherein the second test signal comprises a sampling signal for determining a sampling number of the semiconductor device; and a third pin, configured for transmitting a third test signal of the at least one test signal to the tester of the ATE, wherein the third test signal comprises a testing result. ### Claim 2 (depends on 1) The IC testing interface of claim 1, wherein the processing means converts or sorts the digital signal, calibrates an offset of the digital signal, or takes an arithmetic operation on the digital signal. ### Claim 3 (depends on 1) The IC testing interface of claim 1, wherein the IC testing interface integrates a probe interface board, a load board, or a probe board so as to be installed in the ATE. ### Claim 4 (depends on 1) The IC testing interface of claim 1, wherein each of the plurality of digitizers comprises: an operational amplifier; and an analog to digital converter (ADC), coupled to the operational amplifier. ### Claim 5 (depends on 1) The IC testing interface of claim 1, wherein the processing means is a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), a microprocessor, or a micro-controller. ### Claim 6 (depends on 1) The IC testing interface of claim 1, wherein the IC testing interface is a replaceable interface. ### Claim 7 (depends on 1) The IC testing interface of claim 1, wherein the semiconductor device is a liquid crystal display driver IC. ### Claim 8 (depends on 1) The IC testing interface of claim 1, wherein the connection unit comprises a Universal Serial Bus (USB). ### Claim 9 An automatic test equipment (ATE) for testing a semiconductor device, comprising: a tester; a prober, configured for carrying the semiconductor device; a probe card, coupled to the tester for probing the semiconductor device; and an integrated circuit (IC) testing interface, coupled to the tester and installed outside of the tester, the IC testing interface comprising: at least one pin, configured for receiving or transmitting at least one test signal to the tester; a plurality of digitizers, coupled to the at least one pin for generating a digital signal; a processing means, coupled to the plurality of digitizers for processing the digital signal; and a connection unit, configured for connecting the processing means with a computing device for transmitting an output signal from the processing means to the computing device; wherein the IC testing interface is disposed between the tester and the prober of the ATE; wherein the at least one pin comprises: a first pin, configured for transmitting a first test signal of the at least one test signal to the tester of the ATE, wherein the first test signal comprises an enabling signal for reading or writing a testing datum; a second pin, configured for transmitting a second test signal of the at least one test signal to the tester of the ATE, wherein the second test signal comprises a sampling signal for determining a sampling number of the semiconductor device; and a third pin, configured for transmitting a third test signal of the at least one test signal to the tester of the ATE, wherein the third test signal comprises a testing result. ### Claim 10 (depends on 9) The ATE of claim 9, wherein the processing means converts or sorts the digital signal, calibrates an offset of the digital signal, or takes an arithmetic operation on the digital signal. ### Claim 11 (depends on 9) The ATE of claim 9, wherein the IC testing interface integrates a probe interface board, a load board, or a probe board so as to be installed in the ATE. ### Claim 12 (depends on 9) The ATE of claim 9, wherein each of the plurality of digitizers comprises: an operational amplifier; and an analog to digital converter (ADC), coupled to the operational amplifier. ### Claim 13 (depends on 9) The ATE of claim 9, wherein the processing means is a field-programmable gate array (FPGA), an application specific integrated circuit (ASIC), a microprocessor, or a micro-controller. ### Claim 14 (depends on 9) The ATE of claim 9, wherein the IC testing interface is a replaceable interface. ### Claim 15 (depends on 9) The ATE of claim 9, wherein the semiconductor device is a liquid crystal display driver IC. ### Claim 16 (depends on 9) The IC testing interface of claim 9, wherein the connection unit comprises a Universal Serial Bus (USB).