# US 9,435,860 B2 · Gated state machine circuitry having three clock 2 enable states

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- Number: US 9,435,860 B2
- Document ID: US9435860B2
- Status: Granted
- Kind: B2
- Application number: 14/744,767
- Filed: 2015-06-19
- Published: 2015-10-08
- Granted: 2016-09-06
- Earliest claimed: 2006-02-03
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US9435860B2

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/3172: {Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing}
- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- G01R 31/318572: {Input/Output interfaces}
- G01R 31/318577: {AC testing, e.g. current testing, burn-in}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

## Claims

### Claim 1

Controller circuitry comprising:
A. state machine circuitry having a command 0 input, a command 1 input, a frame marker input, a scan clock input, a test enable input, a clock 2 enable output, a parallel scan enable output, and a serial scan enable output, in response to signals on the command 0 input, the command 1 input, and the frame marker input, and clock signal cycles on the scan clock input, the state machine circuitry having:
i. a first state producing an enable signal on the clock 2 enable output of one clock signal cycle;
ii. a second state producing enable signals on the clock 2 enable output of two clock signal cycles; and
iii. a third state producing enable signals on the clock 2 enable output of three clock signal cycles;
B. first gate circuitry having a first input connected to clock 2 enable output, a second input connected to the scan clock input, and a clock 2 output; and
C. second gate circuitry having a first input connected to the scan clock input, a second input connected to the test enable input, and a clock 1 output.

### Claim 2 (depends on 1)

The controller circuitry of claim 1 including a command lead connected to the command input and a command output of a flip-flop.

### Claim 3 (depends on 1)

The controller circuitry of claim 1 including a frame marker lead connected to the frame marker input and a frame marker output of a flip-flop.

### Claim 4 (depends on 1)

The controller circuitry of claim 1 in which the controller circuitry is included in an integrated circuit and a scan clock lead extends from the scan clock input onto the integrated circuit.

### Claim 5 (depends on 1)

The controller circuitry of claim 1 in which the controller circuitry is included in an integrated circuit and a test enable lead extends from the test enable input onto the integrated circuit.

### Claim 6 (depends on 1)

The controller of claim 1 including scan circuitry and a clock 1 lead connected from the clock 1 output to the scan circuitry.

### Claim 7 (depends on 1)

The controller of claim 1 including scan circuitry and a clock 2 lead connected from the clock 2 output to the scan circuitry.

### Claim 8 (depends on 1)

The controller of claim 1 including scan circuitry and a parallel scan enable lead connected from the parallel scan enable output to the scan circuitry.

### Claim 9 (depends on 1)

The controller of claim 1 including scan circuitry and a serial scan enable lead connected from the serial scan enable output to the scan circuitry.