# US 9,435,859 B2 · Interposer capture shift update cell between functional and test data

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- Number: US 9,435,859 B2
- Document ID: US9435859B2
- Status: Granted
- Kind: B2
- Application number: 14/612,748
- Filed: 2015-02-03
- Published: 2015-06-04
- Granted: 2016-09-06
- Earliest claimed: 2011-02-07
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US9435859B2

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/31713: {Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572)}
- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- H10W 72/90: Bond pads, in general
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/07254: {changes in dispositions}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

## Claims

### Claim 1

An integrated circuit interposer comprising:
A. a substrate having a first side and an opposed second side;
B. first functional input pads formed on the first side of the substrate;
C. first functional output pads formed on the second side of the substrate and coupled to the first functional input pads;
D. second functional input pads formed on the second side of the substrate;
E. second functional output pads formed on the first side of the substrate and coupled to the second functional input pads;
F. a test data input pad, a test clock input pad, a test mode select input pad, and a test data output pad formed on the first side of the substrate;
G. a test access port controller, formed on the substrate, coupled to the test clock input pad and the test mode select input pad, and having a control output bus; and
H. boundary register circuitry formed on the substrate, the boundary register circuitry including input boundary scan cells, each input boundary scan cell including a functional input coupled to a first functional input pad, a functional output coupled to a first functional output pad, a test data input coupled to the test data input pad, a test data output coupled to the test data output pad, and a control input coupled to the control output bus of the test access port controller, each input boundary scan cell including:
i. a capture shift update cell that is coupled between the functional input and the functional output, the capture shift update cell also being coupled between the test data input and the test data output, and the capture shift update cell also being coupled to the control input, and
ii. multiplexer circuitry that is coupled between the functional input and output and is also coupled between the capture shift update cell and the functional output.

### Claim 2 (depends on 1)

The integrated circuit interposer of claim 1 and a base substrate carrying the integrated circuit interposer, the base substrate having pads connected to the pads on the first side of the integrated circuit interposer substrate.

### Claim 3 (depends on 1)

The integrated circuit interposer of claim 1 and stacked integrated circuit die, carrying functional integrated circuits, coupled to the pads on the second side of the integrated circuit interposer substrate.