# US 9,434,028 B2 · Soldering method and method of manufacturing semiconductor device

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- Number: US 9,434,028 B2
- Document ID: US9434028B2
- Status: Granted
- Kind: B2
- Application number: 14/301,425
- Filed: 2014-06-11
- Published: 2014-12-25
- Granted: 2016-09-06
- Earliest claimed: 2013-06-25
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Akira Iso
- Web page: https://patentgrep.com/patent/US9434028B2

## CPC

- B23K 35/383: {mainly containing noble gases or nitrogen}
- C04B 37/006: {consisting of metals or metal salts}
- C04B 37/026: {consisting of metals or metal salts}
- H10W 40/037: {Assembling together parts thereof}
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- C04B 2235/652: Reduction treatment (C04B2235/664 takes precedence)
- C04B 2237/12: Metallic interlayers
- C04B 2237/121: based on aluminium
- C04B 2237/123: based on iron group metals, e.g. steel
- C04B 2237/124: based on copper
- C04B 2237/36: Non-oxidic
- C04B 2237/402: Aluminium
- C04B 2237/407: Copper
- C04B 2237/55: Pre-treatments of a coated or not coated substrate other than oxidation treatment in order to form an active joining layer
- C04B 2237/72: Forming laminates or joined articles comprising at least two interlayers directly next to each other
- H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)}
- H10W 72/07554: {changes in dispositions}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 76/157: having interconnections parallel to the insulating or insulated base
- H10W 90/00: Package configurations
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- B23K: SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- C04B: LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE {(roofing granules E04D7/005)}; CERAMICS (devitrified glass-ceramics C03C10/00); REFRACTORIES; TREATMENT OF NATURAL STONE
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a soldering method through nickel plating layer to reduce void occurrence rate and a method of manufacturing semiconductor device by using the soldering method. By heating a copper base plate having a nickel plating layer at a temperature range of 300° C. to 400° C. in an inert gas atmosphere beforehand, void occurrence rate can be reduced in soldering the copper base plate to an insulating circuit board.

## Claims

### Claim 1

A soldering method comprising:
heat treating a member having a nickel plating layer including hydrogen in a heat treating temperature range of 300° C. to 400° C. in an inert gas atmosphere, thereby reducing a nickel oxide film on a surface of the nickel plating layer;
disposing a solder between the heat-treated member and a joined member; and
joining the heat-treated member to the joined member with the solder in a reducing gas atmosphere at a second temperature lower than the heat treating temperature.

### Claim 2 (depends on 1)

The soldering method according to claim 1, wherein the nickel plating layer is formed by electroless plating treatment.

### Claim 3 (depends on 1)

The soldering method according to claim 1, wherein the heat treating temperature range is 320° C. to 360° C.

### Claim 4 (depends on 1)

The soldering method according to claim 1, wherein the inert gas is nitrogen gas or argon gas.

### Claim 5 (depends on 1)

The soldering method according to claim 1, wherein the second temperature is in a temperature range of 200° C. to 300° C.

### Claim 6

A method of manufacturing a semiconductor device comprising:
heat treating a base plate having a nickel plating layer including hydrogen in a heat treating temperature range of 300° C. to 400° C. in an inert gas atmosphere, thereby reducing a nickel oxide film on a surface of the nickel plating layer;
disposing a solder between the heat-treated base plate and an insulating circuit board; and
joining the heat-treated base plate to a conductive foil of the insulating circuit board with the solder in a reducing gas atmosphere at a second temperature lower than the heat treating temperature.

### Claim 7 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6, wherein the nickel plating layer is formed by electroless plating treatment.

### Claim 8 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6, wherein the heat treating temperature range is 320° C. to 360° C.

### Claim 9 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6, wherein the conductive foil has a nickel plating layer.

### Claim 10 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6, wherein the inert gas is nitrogen gas or argon gas.

### Claim 11 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6, wherein the base plate comprises copper, aluminum, AISiC, or MgSiC.

### Claim 12 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6, wherein the insulating circuit board comprises a ceramic plate with conductive foils disposed on both sides of the ceramic plate.

### Claim 13 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6, wherein the conductive foil is a copper foil.

### Claim 14 (depends on 6)

The method of manufacturing a semiconductor device according to claim 6, wherein the second temperature is in a temperature range of 200° C. to 300° C.