Wiring substrate and semiconductor package

A wiring substrate comprising:

• an insulating layer that is an outermost layer of the wiring substrate and includes an external exposed surface;
• a pad forming part that is formed on a side of the external exposed surface;
• and
• a pad that projects from the external exposed surface;
• wherein the pad forming part includes
• a recess part that is recessed inward relative to the external exposed surface, and
• a weir part that projects outward relative to the external exposed surface and encompasses the recess part from a plan view,
• wherein the pad includes
• a pad body that is formed within the recess part and the weir part, and
• an eave part that is formed on the weir part and integrally formed with the pad body,
• wherein the pad body includes an end part that projects to the weir part,
• wherein the eave part projects in a horizontal direction from the end part of the pad body,
• wherein the end part of the pad body includes a flat surface, and
• wherein the insulating layer and the weir part are formed of an insulating resin.