Differential signal crosstalk minimization for dual stripline
AssigneeCisco Technology, Inc.
InventorsYongming Xiong, Lin Shen, Shahbaz Mahmood
Life of this patent
Estimating the term…
Abstract
The subject technology provides configurations for a printed circuit board that includes a first reference plane, a first signal layer below the first reference plane, a second signal layer below the first signal layer, a second reference plane below the second signal layer, a first differential pair on the first signal layer, and a second differential pair on the second signal layer, each of the first and second differential pairs comprising, respectively, a first pair and a second pair of conductive traces formed on a dielectric material of the PCB, the first pair of conductive traces being arranged on the dielectric material to interleave with the second pair of conductive traces.
Claims19
A printed circuit board (PCB) comprising:
- a first reference plane;
- a first signal layer below the first reference plane;
- a second signal layer below the first signal layer;
- a second reference plane below the second signal layer;
- a first differential pair of conductive traces on the first signal layer;
- and
- a second differential pair of conductive traces on the second signal layer, the first differential pair arranged to interleave the second differential pair wherein an offset between a first trace of the second differential pair and a second trace of the first differential pair is smaller than an offset between the first trace of the second differential pair and a first trace of the first differential pair.
A system comprising:
- a processor;
- an interface coupled to the processor, the interface including a PCB board, the PCB board comprising:
- a first reference plane;
- a first signal layer below the first reference plane;
- a second signal layer below the first signal layer;
- a second reference plane below the second signal layer;
- a first differential pair of conductive traces on the first signal layer;
- and
- a second differential pair of conductive traces on the second signal layer, the first differential pair arranged to interleave the second differential pair wherein an offset between a first trace of the second differential pair and a second trace of the first differential pair is smaller than an offset between the first trace of the second differential pair and a first trace of the first differential pair.
An apparatus comprising:
- a printed circuit board (PCB), the PCB including:
- a first set of vias and a second set of vias;
- at least one routing channel between the first set of vias and the second set of vias, the at least one routing channel including at least a pair of overlapping conductive traces;
- a first reference plane;
- a first signal layer below the first reference plane;
- a second signal layer below the first signal layer;
- a second reference plane below the second signal layer;
- a first differential pair of conductive traces on the first signal layer;
- and
- a second differential pair of conductive traces on the second signal layer, the first differential pair arranged to interleave the second differential pair wherein an offset between a first trace of the second differential pair and a second trace of the first differential pair is smaller than an offset between the first trace of the second differential pair and a first trace of the first differential pair.
Dependencies are inferred from the claim text.