Backchannel communications for initialization of high-speed networks
AssigneeIntel Corporation
InventorsFrank N. Cornett, Brent R. Rothermel
Life of this patent
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Abstract
One embodiment provides a network controller. The network controller includes a modulation module. The modulation module includes a high rate (HR) bit sequence generator configured to generate a first high rate bit sequence, encoder circuitry configured to encode a first low rate bit stream, the first low rate bit stream comprising backchannel information, and modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence. The network controller further includes transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period.
Claims20
A network controller, comprising:
- a modulation module comprising:
- a high rate (HR) bit sequence generator configured to generate a first HR bit sequence,
- encoder circuitry configured to encode a first low rate (LR) bit stream, the first LR bit stream comprising backchannel information, and
- modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence;
- transmit circuitry configured to transmit the modulated first HR bit sequence to a link partner during a link initialization period;
- and
- demodulation circuitry configured to receive a sequence of receiver bit decisions (RBDs) related to a received modulated second high rate (HR) bit sequence, the modulated second HR bit sequence comprising at least one of a true high rate bit (HRB) and at least one of a complemented HRB.
A method, comprising:
- generating, by a high rate (HR) bit sequence generator, a first HR bit sequence;
- encoding, by encoder circuitry, a first low rate bit stream, the first low rate bit stream comprising backchannel information;
- modulating, by modulation circuitry, the encoded first low rate bit stream onto the first HR bit sequence;
- transmitting, by transmit circuitry, the modulated first HR bit sequence to a link partner during a link initialization period;
- and
- receiving, by demodulation circuitry, a sequence of receiver bit decisions (RBDs) related to a received modulated second high rate (HR) bit sequence, the modulated second high rate (HR) bit sequence comprising at least one of a true high rate bit (HRB) and at least one of a complemented HRB.
A non-transitory computer readable medium having instructions stored thereon, wherein said instructions when executed by one or more processors result in the following operations comprising:
- generating a first high rate bit sequence;
- encoding a first low rate bit stream, the first low rate bit stream comprising backchannel information;
- modulating the encoded first low rate bit stream onto the first HR bit sequence;
- and
- transmitting the modulated first HR bit sequence to a link partner during a link initialization period;
- and
- receiving a sequence of receiver bit decisions (RBDs) related to a received modulated second high rate (HR) bit sequence, the modulated second high rate (HR) bit sequence comprising at least one of a true high rate bit (HRB) and at least one of a complemented HRB.
A node comprising:
- a processor;
- a memory;
- and
- a network controller, comprising:
- a modulation module comprising:
- a high rate (HR) bit sequence generator configured to generate a first HR bit sequence,
- encoder circuitry configured to encode a first low rate (LR) bit stream, the first LR bit stream comprising backchannel information, and
- modulation circuitry configured to modulate the encoded first low rate bit stream onto the first high rate bit sequence;
- transmit circuitry configured to transmit the modulated first high rate bit sequence to a link partner during a link initialization period;
- and
- demodulation circuitry configured to receive a sequence of receiver bit decisions (RBDs) related to a received modulated second high rate (HR) bit sequence, the modulated second HR bit sequence comprising at least one of a true high rate bit (HRB) and at least one of a complemented HRB.
Dependencies are inferred from the claim text.