Partial response decision feedback equalizer with selection circuitry having hold state

An integrated circuit comprising:

• receiver circuitry operable to receive data and to generate one or more sets of samples at corresponding sampler outputs in response to one or more clock signals;
• selection circuitry operable to (a) alternately select between a first sampler circuit output and a prior resolved data signal according to a first timing signal, the selection comprising a first output, (b) alternately select between a second sampler circuit output and the prior resolved data signal according to the first timing signal, the selection comprising a second output, (c) select between the first and second output to generate a third output that represents a signal with a given state responsive to a selection signal;
• and
• wherein the selections for (a) and (b) are constrained to both select the prior resolved data signal before the third output changes state.

A method of operation in a receiver integrated circuit, the method comprising:

• receiving data with a receiver including first and second comparators;
• generating one or more sets of samples with the first and second comparators from the received data at corresponding sampler outputs in response to one or more clock signals;
• (a) alternately selecting, with selection circuitry, between a first sampler circuit output and a prior resolved data signal according to a first timing signal, the selection comprising a first output;
• (b) alternately selecting, with the selection circuitry, between a second sampler circuit output and the prior resolved data signal according to the first timing signal, the selection comprising a second output;
• (c) selecting, with the selection circuitry, between the first and second output to generate a third output that represents a signal with a given state responsive to a selection signal;
• and
• constraining the selections for (a) and (b) to both select the prior resolved data signal before the third output changes state.