Test circuits
AssigneesImec Vzw, Universiteit Gent
InventorsJohan Bauwelinck, Guy Torfs, Yu Ban, Timothy De Keulenaer
Life of this patent
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Abstract
Described herein is a feed forward equalizer that is configured to operate in a normal operational mode and in a test operational mode. The feed forward equalizer has an input port and an output port which are used for the normal operational mode. A test input port and a test output port are provided in the feed forward equalizer, and are used for the test operational mode. Buffers may be provided for matching the impedance of respective ones of the input, output, test input, and test output ports. The feed forward equalizer allows testing during development, and once mounted in an integrated circuit, without interfering with the normal operational mode.
Claims13
A feed forward equalizer circuit comprising:
- an input port for receiving an input signal;
- a first line connected to the input port;
- an output port for providing an output signal;
- a second line connected to the output port;
- a first tap element connected between the first line and the second line at respective line nodes;
- at least one second tap element connected between the first line and the second line at respective line nodes;
- at least one first delay element connected to the first line between the first tap element and the at least one second tap element;
- at least one second delay element connected to the second line between the at least one second tap element and the first tap element;
- a test input port connected to the first line and a test output port connected to the second line, and wherein the test input port and the test output port are respectively connected to first and second line nodes associated with the at least one second tap element.
An integrated circuit including a feed forward equalizer circuit, wherein the feed forward equalizer circuit comprises:
- an input port for receiving an input signal;
- a first line connected to the input port;
- an output port for providing an output signal;
- a second line connected to the output port;
- a first tap element connected between the first line and the second line at respective line nodes;
- at least one second tap element connected between the first line and the second line at respective line nodes;
- at least one first delay element connected to the first line between the first tap element and the at least one second tap element;
- at least one second delay element connected to the second line between the at least one second tap element and the first tap element;
- a test input port connected to the first line and a test output port connected to the second line, and wherein the test input port and the test output port are respectively connected to first and second line nodes associated with the at least one second tap element.
A method of testing a feed forward equalizer circuit comprising an input port for receiving an input signal;
- a first line connected to the input port;
- an output port for providing an output signal;
- a second line connected to the output port;
- a first tap element connected between the first line and the second line at respective line nodes;
- at least one second tap element connected between the first line and the second line at respective line nodes;
- at least one first delay element connected to the first line between the first tap element and the at least one second tap element;
- and at least one second delay element connected to the second line between the at least one second tap element and the first tap element;
- wherein the feed forward equalizer circuit further comprises a test input port connected to the first line and a test output port connected to the second line;
- and the test input port and the test output port are respectively connected to first and second line nodes associated with the at least one second tap element, the method comprising:
- disabling the input port and the output port;
- introducing a test input signal at the test input port into the feed forward equalizer circuit at the first line node associated with the at least one second tap element during testing;
- and
- measuring a test output signal at the test output port.
Dependencies are inferred from the claim text.