Circuit and method for clock and data recovery

A clock and data recovery circuit, comprising:

• a phase locked loop circuit;
• a first phase interpolator which is electrically coupled to the phase locked loop circuit and is configured to generate a first clock signal;
• a second phase interpolator which is electrically coupled to the phase locked loop circuit and is configured to generate a second clock signal, wherein the first clock signal and the second clock signal are different in phase by 90 degrees;
• a sampling module configured to receive an input data, the first clock signal, and the second clock signal and accordingly generate a data signal and an edge signal;
• a serial-to-parallel converter electrically coupled to the sampling module, being configured to generate a parallel data signal and a parallel phase signal based on the data signal and the edge signal;
• a phase detector electrically coupled to the serial-to-parallel converter, and is configured to generate at least one error signal based on the parallel data and phase signals, wherein the serial-to-parallel converter operates at a first operating frequency;
• a filter unit electrically coupled to the phase detector to filter output signals of the phase detector;
• and
• a parallel-to-serial converter electrically coupled to the first phase interpolator and the second phase interpolator, and being configured to convert filtered signals, which are outputted from the filter unit, to serial signals that are outputted to the first interpolator and the second interpolator,
• wherein the first phase interpolator and the second phase interpolator operate at a second operating frequency, and the second operating frequency is higher than the first operating frequency.

A clock and data recovery method, comprising:

• respectively sampling input data according to a first clock signal and a second clock signal to generate a data signal and an edge signal;
• based on the data signal and the edge signal, performing a serial-to-parallel conversion and then detecting a phase difference between a parallel data signal and a parallel phase signal, in order to generate at least one error signal;
• generating first output recovered data and a first phase adjust signal according to the at least one error signal;
• performing a parallel-to-serial conversion on the first output recovered data and the first phase adjust signal in order to generate second output recovered data and a second phase adjust signal;
• and
• adjusting the first clock signal and the second clock signal according to the second output recovered data and the second phase adjust signal.