Continuous-time oversampling pipeline analog-to-digital converter
AssigneeAnalog Devices Global
InventorHajime Shibata
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Abstract
A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.
Claims20
A pipelined analog-to-digital converter (ADC), comprising:
- at least one pipeline stage including:
- a delay unit to generate an analog input current signal representing a delayed version of an analog input voltage signal;
- an encoder circuit including a plurality of encoders to generate a plurality of digital output signals based on the analog input voltage signal and the plurality of interleaved clock signals;
- a decoder circuit including a plurality of decoders to generate a plurality of analog output current signals based on the digital output signals and the plurality of interleaved clock signals;
- and
- a subtraction circuit to generate a residue signal based on the analog input current signal and at least one of the plurality of analog output current signals.
A method of performing an analog-to-digital conversion, comprising:
- delaying, by a delay unit of a pipeline stage, an analog input voltage signal to generate an analog input current signal representing a delayed version of the analog input voltage signal;
- encoding, by a plurality of encoders of an encoder circuit of the pipeline stage, a plurality of digital output signals based on the analog input voltage signal and the plurality of interleaved clock signals;
- decoding, by a plurality of decoders of a decoder circuit of the pipeline stage, the plurality of digital output signals as a function of the plurality of interleaved clock signals to generate a plurality of analog output current signals;
- and
- generating, by a subtraction circuit of the pipeline stage, a residue signal based on the analog input current signal and at least one of the plurality analog output current signals.
A analog-to-digital converter (ADC), comprising:
- means for delaying an analog input voltage signal to generate an analog input current signal representing a delayed version of the analog input voltage signal;
- means for encoding the analog input voltage signal to generate a plurality of digital output signals based on the analog input voltage signal and the plurality of interleaved clock signals;
- means for decoding the plurality of digital output signals as a function of the plurality of interleaved clock signals to generate a plurality of analog output current signals;
- means for subtracting at least one of the plurality of analog output current signals from the analog input current signal to generate a residue signal.
Dependencies are inferred from the claim text.