Mismatch correction of attenuation capacitor in a successive approximation register analog to digital converter

A multi-segment capacitive successive approximation analog to digital converter (SAR ADC) comprising:

• a digital to analog converter (DAC) having a capacitor array, the capacitor array having a plurality of segments, and a number of attenuation capacitors that are connected to the plurality of segments such that an attenuation capacitor is connected to and between each adjacent pair of segments, the plurality of segments including:
• a main DAC segment having a number of binary-weighted main conversion capacitors;
• one or more sub-DAC segments having a number of binary-weighted sub-DAC capacitors;
• a comparator coupled to the DAC;
• and
• a controller coupled to a memory, and to the DAC and to the comparator, in which the controller is operable to:
• determine an error voltage for each of a plurality of most significant bit (MSB) capacitors in the main DAC segment of the multi-segment SAR ADC using a calibration DAC;
• digitize and store in the memory each of the error voltages corresponding to the MSB capacitors to form a set of digitized error voltages;
• and
• calculate and store in the memory an error voltage for each of a plurality of less significant bit (LSB) capacitors in at least the first sub DAC segment by summing the set of digitized error voltages to form a sum of error voltages (sum(e)) and assigning a percentage of the sum(e) as the error voltage for each of the LSB capacitors, such that a mismatch in the attenuation capacitor between the main DAC segment and the first sub DAC segment is mitigated.