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US 9,432,040 B2Granted
Analog-to-digital converter for correcting error and analog-to-digital converting method
AssigneesSK hynix Inc., Industry-University Cooperation Foundation Hanyang University
InventorsJa Seung Gou, Oh Kyong Kwon, Min Kyu Kim
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Abstract
An analog-to-digital converter includes an upper bit conversion unit suitable for receiving an input signal, and sampling upper bits from the input signal, a lower bit conversion unit suitable for receiving a residual voltage remaining after the sampling of the upper bit conversion unit, and sampling lower bits from the residual voltage, and an error correction unit suitable for correcting an error of the sampled upper bits and the sampled lower bits.
Claims17
An analog-to-digital converter comprising:
- an upper bit conversion unit suitable for receiving an input signal, sampling upper bits from the input signal, and outputting a residual voltage remaining after the sampling the upper bits;
- a lower bit conversion unit suitable for receiving the residual voltage from the upper bit conversion unit, and sampling lower bits from the residual voltage;
- and
- an error correction unit suitable for correcting an error of the sampled upper bits and the sampled lower bits;
- wherein the upper bit conversion unit includes a capacitor array having a lowermost capacitor receiving the ramp signal from the lower bit conversion unit,
- wherein the lower bit conversion unit includes a ramp signal generator suitable for generating the ramp signal and applying the ramp signal to the lowermost capacitor, when sampling the lower bits.
3 more elements
An analog-to-digital converter comprising:
- an SAR analog-to-digital converter suitable for sampling upper bits from an input signal and outputting a residual voltage remaining after the sampling the upper bits;
- a single slope analog-to-digital converter suitable for sampling lower bits from the residual voltage;
- and
- an error correction unit suitable for correcting an error of the sampled upper bits and the sampled lower bits:
- wherein the SAR analog-to-digital converter includes a capacitor array having a lowermost capacitor receiving the ramp signal from the lower bit conversion unit,
- wherein the SS analog-to-digital converter includes a ramp signal generator suitable for generating the ramp signal and applying the ramp signal to the lowermost capacitor, when sampling the lower bits.
3 more elements
Dependencies are inferred from the claim text.