Clock data recovery circuit and a method of operating the same

A method of operating a clock data recovery circuit, the method comprising:

• generating an automatic process compensation (APC) code, which regulates a frequency change per bit of an automatic frequency control (AFC) code;
• generating the AFC code which enables a frequency of a recovery clock signal to approach a target frequency;
• and
• performing a phase tracking to make a phase of the recovery clock signal approach a phase of serial data based on an up fine tuning code and a down fine tuning code.

A clock data recovery circuit, comprising:

• an automatic process compensation (APC) circuit configured to generate an APC code;
• an automatic frequency control (AFC) circuit configured to generate an AFC code, a proportional path gain and an integral path gain;
• a digital loop filter configured to generate up and down fine codes by using an up phase error count signal and a down phase error count signal according to the integral path gain and the proportional path gain;
• a loop combiner configured to generate up and down fine tuning codes based on up and down phase error signals and the up and down fine codes;
• and
• a digitally controlled oscillator configured to generate a recovery clock signal whose frequency is controlled by the APC code, the AFC code, and the up and down fine tuning codes.