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US 9,432,025 B1Granted
Techniques for reducing skew between clock signals
AssigneeAltera Corporation
InventorChuan Thim Khor
Life of this patent
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Abstract
A clock signal generation circuit generates a first clock signal based on second and third clock signals. The clock signal generation circuit generates an indication of a phase difference between the second and the third clock signals. A skew reduction circuit reduces skew between the second and the third clock signals in response to the indication of the phase difference between the second and the third clock signals indicating that the second and the third clock signals are aligned in phase within at least an error margin of the clock signal generation circuit.
Claims20
A circuit comprising:
- a clock signal generation circuit to generate a first clock signal based on second and third clock signals, wherein the clock signal generation circuit generates an indication of a phase difference between the second and the third clock signals;
- and
- a skew reduction circuit to reduce skew between the second and the third clock signals in response to the indication of the phase difference between the second and the third clock signals indicating that the second and the third clock signals are aligned in phase within at least an error margin of the clock signal generation circuit.
A circuit comprising:
- a clock signal generation circuit to generate a first clock signal based on second and third clock signals, wherein the clock signal generation circuit generates an indication of a phase difference between the second and the third clock signals;
- and
- a skew reduction circuit to generate an indication of a skew between the second and the third clock signals in response to the indication of the phase difference between the second and the third clock signals indicating that the second and the third clock signals are aligned in phase within at least an error margin, wherein the skew reduction circuit reduces the skew between the second and the third clock signals based on the indication of the skew between the second and the third clock signals.
A method comprising:
- generating a first clock signal based on second and third clock signals using a clock signal generation circuit;
- generating an indication of a phase difference between the second and the third clock signals using the clock signal generation circuit;
- generating an indication of a skew between the second and the third clock signals in response to the indication of the phase difference between the second and the third clock signals indicating that the second and the third clock signals are aligned in phase within at least an error margin using a skew reduction circuit;
- and
- reducing the skew between the second and the third clock signals based on the indication of the skew between the second and the third clock signals using the skew reduction circuit.
2 more elements
Dependencies are inferred from the claim text.