Back to results
US 9,432,022 B2Granted
Wide-range level-shifter
AssigneeQUALCOMM Incorporated
InventorsChangho Jung, Frank Guo, Rakesh Vattikonda
Life of this patent
Estimating the term…
Abstract
A level-shifter is provided with PMOS stacks that are selectively weakened or strengthened depending upon the binary state of an input signal.
Claims19
A level-shifter, comprising:
- a pair of cross-coupled transistors;
- wherein a first one of the cross-coupled transistors has a first terminal coupled to a first node and a gate coupled to an output node, and wherein a remaining second one of the cross-coupled transistors has a gate coupled to the first node and a first terminal coupled to the output node;
- a first pull-up transistor configured to be responsive to a first control signal to selectively couple a second terminal of the first cross-coupled transistor to a power supply node providing a first power supply voltage;
- a second pull-up transistor configured to be responsive to a second control signal to selectively couple a second terminal of the second cross-coupled transistor and the power supply node;
- and
- a control circuit configured to control the first control signal and the second control signal to switch on the first pull-up transistor and to switch off the second pull-up transistor responsive to a discharge of the first node and a charge of the output node to the first power supply voltage and to switch on the second pull-up transistor and switch off the first pull-up transistor responsive to a discharge of the output node and a charge of the first node to the first power supply voltage;
- a first pull-down transistor having a terminal coupled to the first node, the first pull-down transistor having its gate coupled to an input signal node;
- an inverter coupled between the input signal node and an inverted input signal node, the inverter being configured to charge the inverted input signal node to a second power supply voltage responsive to the input signal node being discharged;
- and
- a second pull-down transistor coupled to the output node, the second pull-down transistor having its gate coupled to the inverted input signal node, wherein the control circuit includes a third pull-down transistor having its gate coupled to the output node and a terminal coupled to the gate of the first pull-up transistor, the third pull-down transistor being configured to discharge the gate of the first pull-up transistor responsive to the output node being charged to the first power supply voltage.
7 more elements
A method, comprising:
- discharging a first node supplying an output signal responsive to an input signal transitioning from a first power supply voltage to ground, wherein the first node couples to a first terminal of a cross-coupled transistor;
- switching on a first pull-up transistor responsive to the input signal transitioning to ground to charge a second terminal of the cross-coupled transistor to a second power supply voltage;
- conducting a current through the switched-on first pull-up transistor and the cross-coupled transistor to charge the first node and the output signal to the second power supply voltage responsive to the input signal transitioning to the first power supply voltage;
- and
- after the charging of the first node and the output signal, switching off the first pull-up transistor such that the discharging of the first node responsive to the input signal transitioning to ground is not opposed by the first pull-up transistor;
- discharging a second node responsive to the input signal transitioning to the first power supply voltage;
- switching on a second pull-up transistor responsive to the input signal transitioning to the first power supply voltage;
- using the switched-on second pull-up transistor to charge the second node to the second power supply voltage responsive to the input signal transitioning to ground;
- and
- after the charging of the second node, switching off the second pull-up transistor such that the discharging of the second node responsive to the input signal transitioning to the first power supply voltage is not opposed by the second pull-up transistor, wherein switching off the first pull-up transistor comprises switching on a third pull-up transistor responsive to the discharging of the second node to charge a control signal driving a gate of the first pull-up transistor.
7 more elements
A level-shifter, comprising:
- a first pull-down transistor having a gate coupled to an input signal node carrying an input signal and a terminal coupled to a first node, the first pull-down transistor being configured to discharge the first node responsive to the input signal transitioning to a first power supply voltage;
- a second pull-down transistor having a gate coupled to an inverted input signal node and a terminal coupled to a output node for supplying an output signal, the second pull-down transistor being configured to discharge the output node and the output signal responsive to a voltage for the inverted input signal node transitioning to the first power supply voltage;
- a first cross-coupled transistor having a gate coupled to the first node and a first terminal coupled to the output node;
- a first pull-up transistor having a first terminal coupled to a second terminal of the first cross-coupled transistor and having a second terminal coupled to a node configured to supply a second power supply voltage that is greater than the first power supply voltage;
- and
- a means for controlling the first pull-up transistor so that the first pull-up transistor is switched on to charge the output node through the first coupled transistor to the second power supply voltage responsive to a charging of the first node to the first power supply voltage and so that the first pull-up transistor is switched off responsive to the discharging of the first node, wherein the first pull-up transistor has a source coupled to a power supply node for supplying the second power supply voltage, the level-shifter further comprising a weak keeper transistor configured to weakly charge a drain of the first pull-up transistor to the second power supply voltage, and wherein the weak keeper transistor comprises a pair of serially-coupled weak keeper PMOS transistors having their gates coupled to the inverted input signal node.
3 more elements
Dependencies are inferred from the claim text.