US 9,432,012 B2Granted

Delay line circuits and semiconductor integrated circuits

AssigneeVia Alliance Semiconductor Co., Ltd.

InventorsQuanfeng Liu, Huijie Duan

Life of this patent

Estimating the term…

Loading patent…

Abstract

A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.

Claims14

Dependent claims

A delay line circuit comprising:

a fine delay unit having an input terminal coupled to an input terminal of the delay line circuit and an output terminal coupled to an output terminal of the delay line circuit through a switch;
and
a coarse delay unit coupled to the output terminal of the fine delay unit in series, wherein the coarse delay unit is coupled to the output terminal of the delay line circuit through a corresponding one of a plurality of first switches,
wherein the fine delay unit comprises a fine delay circuit, and the fine delay circuit comprises:
a first PMOS transistor;
a plurality of second PMOS transistors coupled between a power voltage and a source of the first PMOS transistor in parallel, wherein widths of gate features of the second PMOS transistor are equal;
at least one third PMOS transistor coupled between the power voltage and the source of the first PMOS transistor, wherein a width of gate features of the at least one third PMOS transistor is smaller than the widths of the gate features of the second PMOS transistors;
a second NMOS transistor;
a plurality of second NMOS transistors coupled between a ground voltage and a source of the first NMOS transistor, wherein widths of gate features of the second NMOS transistors are equal;
and
at least one third NMOS transistor coupled between the ground voltage and the source of the first NMOS transistor, wherein a width of gate features of the at least one third NMOS transistor is smaller than the widths of the gate features of the second NMOS transistors.

8 more elements

A semiconductor integrated circuit comprising:

a plurality of core transistors, wherein gate features of the core transistors are arranged in parallel;
and
a circuit module comprising a plurality of semiconductor devices, wherein the semiconductor devices comprises:
a substrate;
an N-type well disposed on the substrate;
a first active region disposed in the N-type well;
a plurality of first sources formed in the first active region;
a plurality of first drains formed in the first active region;
a plurality of first gate features, wherein each first gate feature is disposed on the first active region between one of the first sources and one of the first drains, and the first gate features are arranged in parallel;
a second active region disposed in the N-type well and paralleling the first active region;
a plurality of second sources formed in the second active region;
a plurality of second drains formed in the second active region;
and
a plurality of second gate features, wherein each second gate feature is disposed on the second active region between one of the second sources and one of the second drains, and the second gate features are arranged in parallel,
wherein widths of the first gate features are larger than widths of the second gate features.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/607,230Filed 28 Jan 2015 · division
Priority: CN 2014 1 023593929 May 2014
Published: US 2015/0349765 A13 Dec 2015
Granted: 30 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03K 5/14
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: by the use of delay lines
H10D 84/85
Of only insulated-gate FETs [IGFET]: complementary IGFETs, e.g. CMOS
H10W 20/43
Characterised by their conductive parts: layouts of interconnections
H10D 84/83138
Of only insulated-gate FETs [IGFET]: the IGFETs characterised by having different shapes or dimensions of their gate conductors

Family

Application14/587,628Parent of this division · filed 31 Dec 2014
US 2015/0349766 A1Pre-grant publication · published 3 Dec 2015
US 2015/0349765 A1Published application
US 9,467,130 B2Related patent
US 9,432,012 B2This patent

From the US filing history. Foreign family members aren’t listed.