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US 9,432,010 B2Granted
Buffer control circuit and multi-chip package including the same
AssigneeSK hynix Inc.
InventorJae-Bum Ko
Life of this patent
Estimating the term…
Abstract
A buffer control circuit includes: an activation control block suitable for generating a buffer activation control signal by detecting a first input of a repeatedly provided chip select signal; and a buffer suitable for buffering the chip select signal in response to the buffer activation control signal after the generation of the buffer activation control signal.
Claims11
A buffer control circuit, comprising:
- an activation control block suitable for generating a buffer activation control signal by detecting a first input of a repeatedly provided chip select signal;
- and
- a buffer suitable for buffering the chip select signal in response to the buffer activation control signal after the generation of the buffer activation control signal,
- wherein the activation control block generates the buffer activation control signal, which is enabled a predetermined time after the first input of the chip select signal,
- wherein the activation control block includes:
- a shift unit suitable for generating a plurality of control signals in response to a clock signal by sequentially shifting the chip select signal;
- a latch unit suitable for latching the chip select signal and the control signals in response to a last one among the control signals;
- a clock control unit suitable for generating a plurality of clock signals having different enabling time sections in response to an output signal of the latching unit;
- an input control signal generation unit suitable for generating a plurality of input control signals by sequentially shifting the chip select signal in response to the plurality of clock signals;
- and
- an activation control signal generation unit suitable for generating the buffer activation control signal by detecting rising and falling edges of each of the input control signals.
8 more elements
A multi-chip package, comprising:
- a master chip;
- a plurality of slave chips stacked in an upper portion of the master chip;
- and
- a through-silicon via suitable for transmitting a signal between the master chip and the slave chips,
- wherein the master chip includes a plurality of command input blocks suitable for detecting normal input of a plurality of chip select signals, and transferring the plurality of chip select signals to the plurality of slave chips,
- wherein the plurality of chip select signals are repeatedly inputted,
- wherein each of the command input blocks includes:
- an activation control block suitable for generating a buffer activation control signal by detecting a first input of a repeatedly provided chip select signal;
- and
- a buffer suitable for buffering the chip select signal in response to the buffer activation control signal after the generation of the buffer activation control signal,
- wherein the activation control block generates the buffer activation control signal, which is enabled a predetermined time after the first input of the chip select signal,
- wherein the activation control block includes:
- a shift unit suitable for generating a plurality of control signals in response to a clock signal by sequentially shifting the chip select signal;
- a latch unit suitable for latching the chip select signal and the control signals in response to a last one among the control signals;
- a clock control unit suitable for generating a plurality of clock signals having different enabling time sections in response to an output signal of the latching unit;
- an input control signal generation unit suitable for generating a plurality of input control signals by sequentially shifting the chip select signal in response to the plurality of clock signals;
- and
- an activation control signal generation unit suitable for generating the buffer activation control signal by detecting rising and falling edges of each of the input control signals.
15 more elements
A semiconductor system, comprising:
- a first device suitable for successively providing activation information two or more times;
- and
- a second device suitable for generating an activation control signal in response to the activation information, and performing an operation in response to the activation control signal,
- wherein the second device is a semiconductor memory.
1 more element
Dependencies are inferred from the claim text.