Variable delay element

A delay circuit comprising:

• an input node;
• an output node;
• a p-type silicon on insulator (SOI) transistor having a gate coupled to the input node, a first source/drain region coupled to a first supply voltage node, and a second source/drain region coupled to the output node;
• an n-type SOI transistor having a gate coupled to the input node, a first source/drain region coupled to a second supply voltage node, and a second source/drain region coupled to the output node;
• and
• a biasing circuit having a first delay control output coupled to a back gate of the p-type SOI transistor and a second delay control output coupled to a back gate of the n-type SOI transistor;
• wherein the first source/drain region and the second source/drain region of the n-type SOI transistor are separated by a channel region;
• wherein the first source/drain region, the second source/drain region, and the channel region of the n-type SOI transistor are disposed on an oxide layer;
• wherein the oxide layer is disposed on a p-type well that forms the back gate of the n-type SOI transistor;
• wherein the p-type well is disposed in an n-type well;
• and
• wherein the n-type well is disposed in a substrate.

A method of operating a delay circuit, the method comprising:

• generating first and second differential control voltages;
• applying the first differential control voltage to a further control node of a first transistor and further control node of a third transistor having a first conductivity type, the first transistor and the third transistor having control nodes coupled to an input node of the delay circuit, a first main current node of the first transistor coupled to a first supply voltage, and a second main current node of the first transistor coupled to an output node of the delay circuit through the third transistor;
• applying the second differential control voltage to a further control node of a second transistor and a further control node of a fourth transistor having a second conductivity type, the second transistor and the fourth transistor having control nodes coupled to the input node, a first main current node of the second transistor coupled to a second supply voltage, and a second main current node of the second transistor coupled to the output node through the fourth transistor;
• and
• applying an input signal to the input node, wherein an output signal carried at the output node is based upon the input signal and has a delay time based on the first and second differential control voltages.

A method of operating a delay circuit, the method comprising:

• generating first and second differential control voltages;
• applying the first differential control voltage to a back gate of an n-type SOI transistor, the n-type SOI transistor having a gate coupled to an input node of the delay circuit, a first source/drain region coupled to a first supply voltage, and a second source/drain region coupled to an output node of the delay circuit;
• applying the second differential control voltage to a back gate of a p-type SOT transistor, the p-type SOI transistor having a gate coupled to the input node, a first source/drain region coupled to a second supply voltage, and a second source/drain region coupled to the output node;
• and
• applying an input signal to the input node, wherein an output signal carried at the output node is based upon the input signal and has a delay time based on the first and second differential control voltages;
• wherein the first source/drain region and the second source/drain region of the n-type SOI transistor are separated by a channel region;
• wherein the first source/drain region, the second source/drain region, and the channel region of the n-type SOI transistor are disposed on an oxide layer;
• wherein the oxide layer is disposed on a p-type well that forms the back gate of the n-type SOI transistor;
• wherein the p-type well is disposed in an n-type well;
• and
• wherein the n-type well is disposed in a substrate.