# US 9,432,007 B1 · Out-of-band (OOB) detection circuit for serial/deserializer (SERDES)

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- Number: US 9,432,007 B1
- Document ID: US9432007B1
- Status: Granted
- Kind: B1
- Application number: 14/461,223
- Filed: 2014-08-15
- Granted: 2016-08-30
- Earliest claimed: 2014-08-15
- Assignees: Xilinx, Inc.
- Applicants: Xilinx, Inc.
- Inventors: Jingfeng Gong; Cheng-Hsiang Hsieh
- Web page: https://patentgrep.com/patent/US9432007B1

## CPC

- H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08)
- H03K 5/2481: {with at least one differential stage}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An out-of-band (OOB) detection circuit includes: a positive input node; a negative input node; a resistive circuit comprising a first resistor coupled between a first supply node and a first node, a variable resistor coupled between the first node and a second node, and a second resistor coupled between the second node and a ground; a first comparator configured to compare a difference between a positive input signal received at the positive input node and a negative input signal received at the negative input node against a positive threshold value, and a second comparator configured to compare the difference between the positive input signal received at the positive input node and the negative input signal received at the negative input node against a negative threshold value.

## Claims

### Claim 1

An out-of-band (OOB) detection circuit, comprising:
a positive input node;
a negative input node;
a resistive circuit coupled between a first supply node and a ground, the resistive circuit including a first node outputting a positive threshold value and a second node outputting a negative threshold value;
a first comparator configured to compare a difference between a positive input signal received at the positive input node and a negative input signal received at the negative input node against the positive threshold value
a first transistor having a gate coupled to the positive input node,
a second comparator configured to compare the difference between the positive input signal received at the positive input node and the negative input signal received at the negative input node against the negative threshold value
first and second gain stages coupled to outputs of the first and second comparators, respectively;
an OR gate coupled to outputs of the first and second gain stages; and
a detection filter coupled to an output of the OR gate, the detection filter comprising:
a first NOR gate having a first input coupled to a clock signal;
a second NOR gate having a first input coupled to the output of the OR gate;
a third NOR gate having a first input coupled to the output of the OR gate;
a fourth NOR gate having a first input coupled to an inverse of the clock signal;
wherein an output of the first NOR gate is coupled to a second input of the second NOR gate, and an output of the second NOR gate is coupled to a second input of the first NOR gate;
wherein an output of the third NOR gate is coupled to a second input of the fourth NOR gate, and an output of the fourth NOR gate is coupled to a second input of the third NOR gate;
a first multiplexer having a first input coupled to the output of the first NOR gate and driven by the clock signal;
a second multiplexer having a first input coupled to the output of the fourth NOR gate and driven by the inverse of the clock signal;
a first inverter having an input coupled to an output of the first multiplexer;
a second inverter having an input coupled to an output of the first inverter and an output coupled to a second input of the first multiplexer;
a third inverter having an input coupled to an output of the second multiplexer;
a fourth inverter having an input coupled to an output of the third inverter and an output coupled to a second input of the second multiplexer; and
a third multiplexer coupled having a first input coupled to the output of the second inverter and a second input coupled to the output of the fourth inverter.

### Claim 2 (depends on 1)

The OOB detection circuit of claim 1:
wherein the first comparator comprises a first transistor having a gate coupled to the positive input node, a second transistor having a gate coupled to the negative input node, a third transistor having a gate coupled to the second node, and a fourth transistor having a gate coupled to the first node;
wherein the second comparator comprises a fifth transistor having a gate coupled to the negative input node, a sixth transistor having a gate coupled to the positive input node, a seventh transistor having a gate coupled to the second node, and an eighth transistor having a gate coupled to the first node;
wherein a drain of the first transistor is coupled to a drain of the third transistor, a drain of the second transistor is coupled to a drain of the fourth transistor, a source of the first transistor is coupled to a source of the second transistor, and a source of the third transistor is coupled to a source of the fourth transistor; and
wherein a drain of the fifth transistor is coupled to a drain of the seventh transistor, a drain of the sixth transistor is coupled to a drain of the eighth transistor, a source of the fifth transistor is coupled to a source of the sixth transistor, and a source of the seventh transistor is coupled to a source of the eighth transistor.

### Claim 3 (depends on 2)

The OOB detection circuit of claim 2, wherein:
the first gain stage includes a negative input coupled to the drain of the first transistor and the drain of the third transistor and a positive input coupled to the drain of the second transistor and the drain of the fourth transistor; and
the second gain stage includes a positive input coupled to the drain of the fifth transistor and the drain of the seventh transistor and a negative input coupled to the drain of the sixth transistor and the drain of the eighth transistor.

### Claim 4 (depends on 3)

The OOB detection circuit of claim 3, further comprising:
a first loading resistor coupled between the first supply node and the negative input of the first gain stage;
a second loading resistor coupled between the first supply node and the positive input of the first gain stage;
a third loading resistor coupled between the first supply node and the positive input of the second gain stage; and
a fourth loading resistor coupled between the first supply node and the negative input of the second gain stage.

### Claim 5 (depends on 2)

The OOB detection circuit of claim 2, further comprising:
a first biasing transistor coupled between the source of the first transistor and the ground;
a second biasing transistor coupled between the source of the third transistor and the ground;
a third biasing transistor coupled between the source of the fifth transistor and the ground; and
a fourth biasing transistor coupled between the source of the seventh transistor and the ground;
wherein a biasing voltage is coupled to a gate of the first biasing transistor, a gate of the second biasing transistor, a gate of the third biasing transistor and a gate of the fourth biasing transistor.

### Claim 6 (depends on 3)

The OOB detection circuit of claim 3, further comprising:
a first capacitor coupled between the gate of the first transistor and the drain of the second transistor;
a second capacitor coupled between the gate of the second transistor and the drain of the first transistor;
a third capacitor coupled between the gate of the fifth transistor and the drain of the sixth transistor; and
a fourth capacitor coupled between the gate of the sixth transistor and the drain of the fifth transistor.

### Claim 7 (depends on 3)

The OOB detection circuit of claim 3, further comprising:
a first loading transistor coupled between the negative input of the first gain stage and a second supply node;
a second loading transistor coupled between the positive input of the first gain stage and the second supply node;
a third loading transistor coupled between the positive input of the second gain stage and the second supply node; and
a fourth loading transistor coupled between the negative input of the second gain stage and the second supply node.

### Claim 8 (depends on 1)

The OOB detection circuit of claim 1, further comprising:
an asymmetric digital filter coupled to an output of the detection filter.

### Claim 9

An out-of-band (OOB) detection circuit, comprising:
a positive input node;
a negative input node;
a resistive circuit coupled between a first supply node and ground, the resistive circuit including a first node outputting a positive threshold value and a second node outputting a negative threshold value;
an initial gain stage coupled to the positive input node and the negative input node
a first comparator coupled to compare a differential output of the initial gain stage to the positive threshold value
a second comparator coupled to compare the differential output of the initial gain stage to the negative threshold value
first and second gain stages coupled to outputs of the first and second comparators, respectively;
an OR gate coupled to outputs of the first and second gain stages; and
a detection filter coupled to an output of the OR gate, the detection filter comprising:
a first NOR gate having a first input coupled to a clock signal;
a second NOR gate having a first input coupled to the output of the OR gate;
a third NOR gate having a first input coupled to the output of the OR gate;
a fourth NOR gate having a first input coupled to an inverse of the clock signal;
wherein an output of the first NOR gate is coupled to a second input of the second NOR gate, and an output of the second NOR gate is coupled to a second input of the first NOR gate;
wherein an output of the third NOR gate is coupled to a second input of the fourth NOR gate, and an output of the fourth NOR gate is coupled to a second input of the third NOR gate;
a first multiplexer having a first input coupled to the output of the first NOR gate and driven by the clock signal;
a second multiplexer having a first input coupled to the output of the fourth NOR gate and driven by the inverse of the clock signal;
a first inverter having an input coupled to an output of the first multiplexer;
a second inverter having an input coupled to an output of the first inverter and an output coupled to a second input of the first multiplexer;
a third inverter having an input coupled to an output of the second multiplexer;
a fourth inverter having an input coupled to an output of the third inverter and an output coupled to a second input of the second multiplexer; and
a third multiplexer coupled having a first input coupled to the output of the second inverter and a second input coupled to the output of the fourth inverter.

### Claim 10 (depends on 9)

The OOB detection circuit of claim 9:
wherein the first comparator comprises a first transistor having a gate coupled to a drain of the second gain transistor, a second transistor having a gate coupled to a drain of the first gain transistor, a third transistor having a gate coupled to the second node, and a fourth transistor having a gate coupled to the first node;
wherein the second comparator comprises a fifth transistor having a gate coupled to the drain of the second gain transistor, a sixth transistor having a gate coupled to the drain of the first gain transistor, a seventh transistor having a gate coupled to the second node, and an eighth transistor having a gate coupled to the first node;
wherein a drain of the first transistor is coupled to a drain of the third transistor, a drain of the second transistor is coupled to a drain of the fourth transistor, a source of the first transistor is coupled to a source of the second transistor, and a source of the third transistor is coupled to a source of the fourth transistor; and
wherein a drain of the fifth transistor is coupled to a drain of the seventh transistor, a drain of the sixth transistor is coupled to a drain of the eighth transistor, a source of the fifth transistor is coupled to a source of the sixth transistor, and a source of the seventh transistor is coupled to a source of the eighth transistor.

### Claim 11 (depends on 10)

The OOB detection circuit of claim 10, wherein:
the first gain stage includes a negative input coupled to the drain of the first transistor and the drain of the third transistor and a positive input coupled to the drain of the second transistor and the drain of the fourth transistor; and
the second gain stage includes a positive input coupled to the drain of the fifth transistor and the drain of the seventh transistor and a negative input coupled to the drain of a sixth transistor and the drain of the eighth transistor.

### Claim 12 (depends on 11)

The OOB detection circuit of claim 11, further comprising:
a first capacitor coupled between the gate of the first transistor and the drain of the second transistor;
a second capacitor coupled between the gate of the second transistor and the drain of the first transistor;
a third capacitor coupled between the gate of the fifth transistor and the drain of the sixth transistor; and
a fourth capacitor coupled between the gate of the sixth transistor and the drain of the fifth transistor.

### Claim 13 (depends on 11)

The OOB detection circuit of claim 11, further comprising:
a first loading resistor coupled between the first supply node and the negative input of the first gain stage;
a second loading resistor coupled between the first supply node and the positive input of the first gain stage;
a third loading resistor coupled between the first supply node and the positive input of the second gain stage; and
a fourth loading resistor coupled between the first supply node and the negative input of the second gain stage.

### Claim 14 (depends on 10)

The OOB detection circuit of claim 10, further comprising:
a first biasing transistor coupled between a source of the first transistor and the ground;
a second biasing transistor coupled between a source of the third transistor and the ground;
a third biasing transistor coupled between a source of the fifth transistor and the ground; and
a fourth biasing transistor coupled between a source of the seventh transistor and the ground;
wherein a biasing voltage is coupled to a gate of the first biasing transistor, a gate of the second biasing transistor, a gate of the third biasing transistor and a gate of the fourth biasing transistor.

### Claim 15 (depends on 9)

The OOB detection circuit of claim 9, further comprising:
an asymmetric digital filter coupled to an output of the detection filter.

### Claim 16 (depends on 1)

The OOB detection circuit of claim 1, wherein the resistive circuit comprises:
a first fixed resistor coupled between the first supply node and the first node, a variable resistor coupled between the first node and a second node, and a second fixed resistor coupled between the second node and ground.

### Claim 17 (depends on 9)

The OOB detection circuit of claim 9, wherein the resistive circuit comprises:
a first fixed resistor coupled between the first supply node and the first node, a variable resistor coupled between the first node and a second node, and a second fixed resistor coupled between the second node and ground.

### Claim 18

An apparatus, comprising:
an out-of-band (OOB) detection circuit coupled to a positive input node and a negative input node, the OOB detection circuit including an output providing either a present signal or an absent signal in response to a differential voltage at the positive and negative input nodes; and
a detection filter, coupled to the output of the OOB detection circuit, the detection filter comprising:
a first NOR gate having a first input coupled to a clock signal;
a second NOR gate having a first input coupled to the output of the OR gate;
a third NOR gate having a first input coupled to the output of the OR gate;
a fourth NOR gate having a first input coupled to an inverse of the clock signal;
wherein an output of the first NOR gate is coupled to a second input of the second NOR gate, and an output of the second NOR gate is coupled to a second input of the first NOR gate;
wherein an output of the third NOR gate is coupled to a second input of the fourth NOR gate, and an output of the fourth NOR gate is coupled to a second input of the third NOR gate;
a first multiplexer having a first input coupled to the output of the first NOR gate and driven by the clock signal;
a second multiplexer having a first input coupled to the output of the fourth NOR gate and driven by the inverse of the clock signal;
a first inverter having an input coupled to an output of the first multiplexer;
a second inverter having an input coupled to an output of the first inverter and an output coupled to a second input of the first multiplexer;
a third inverter having an input coupled to an output of the second multiplexer;
a fourth inverter having an input coupled to an output of the third inverter and an output coupled to a second input of the second multiplexer; and
a third multiplexer coupled having a first input coupled to the output of the second inverter and a second input coupled to the output of the fourth inverter.