Buffer circuit and system having the same

A buffer circuit comprising:

• the power supply voltage detection block configured to detect a level of a power supply voltage;
• a bias generation block configured to generate a plurality of enable bias signals based on the detection of the level of a power supply voltage, and a constant bias signal, which has a level change range more insensitive to a variation in the level of the power supply voltage than the enable bias signals;
• and
• an input buffer configured to amplify an input signal in response to the plurality of enable bias signals and the constant bias signal.

A system comprising:

• a power supply voltage detection block configured to detect a voltage level of a power supply voltage;
• a bias generation block configured to generate a constant bias signal and a plurality of enable bias signals based on a detection result of the power supply voltage detection block;
• and
• an input buffer configured to amplify an input signal in response to the constant bias signal and the plurality of enable bias signals,
• wherein the input buffer comprises first and second enable units, and wherein the first enable unit forms a current path when the power supply voltage is different from a normal level, and the second enable unit forms a current path when the power supply voltage has the normal level.