Low power buffer with gain boost

A buffer circuit comprising:

• a first input node to receive a first input signal;
• a second input node to receive a second input signal;
• a first connection node;
• a second connection node;
• a first supply node;
• a second supply node;
• a first transistor coupled to the first input node, the first supply node, and the first connection node;
• a second transistor coupled to the second input node and the first connection node;
• a third transistor coupled to the second input node, the second supply node, and the second connection node;
• and
• a fourth transistor coupled to the first input node and the second connection node;
• wherein the second input signal is a complement of the first input signal,
• wherein the first transistor, the second transistor and the first bias circuit have a respective plurality of design attributes, and wherein at least one of the respective plurality of design attributes is established to achieve a gain equal to a target gain, the gain being defined by an output amplitude of an output signal at the first connection node divided by an input amplitude of the first input signal, and
• wherein the target gain is one.

A buffer circuit comprising:

• a first input node to receive a first input signal;
• a second input node to receive a second input signal;
• a first connection node;
• a second connection node;
• a third connection node;
• a fourth connection node;
• a first supply node;
• a second supply node;
• a first transistor coupled to the first input node, the first supply node, and the first connection node;
• a second transistor coupled to the second input node and the first connection node;
• a third transistor coupled to the second input node, the second supply node, and the second connection node;
• a fourth transistor coupled to the first input node and the second connection node;
• a fifth transistor coupled to the first connection node, the first supply node, and the third connection node;
• a sixth transistor coupled to the first input node and the third connection node;
• a seventh transistor coupled to the second connection node, the second supply node, and the fourth connection node;
• an eighth transistor coupled to the second input node and the fourth connection node;
• a first bias circuit coupled to the second transistor;
• a second bias circuit coupled to the fourth transistor;
• a third bias circuit coupled to the sixth transistor;
• and
• a fourth bias circuit coupled to the eighth transistor;
• wherein the second input signal is a complement of the first input signal.