US 9,431,988 B2Granted

Stacked chip device

AssigneeInnochips Technology Co., Ltd.

InventorsIn Kil Park, Tae Hyung Noh, Gyeong Tae Kim, Tae Geun Seo, Myung Ho Lee, Min Soo Lee

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Abstract

The present disclosure relates to a stacked chip device including a first stack unit comprising a plurality of electrode patterns respectively disposed for a unit device region and common electrode patterns formed to be connected to cross the unit device regions, a second stack unit disposed on a top portion of the first stack unit and comprising a plurality of first conductor patterns, and a third stack unit disposed on a bottom portion of the first stack unit and comprising a plurality of second conductor patterns, wherein the first and second conductor patterns are formed on a plurality of sheets, the first and second conductor patterns formed on one sheet are formed across a plurality of unit device regions, and the first and second conductor patterns are connected vertically through vias formed penetrating through at least some of the sheets.

Claims14

Dependent claims

A stacked chip device comprising:

a first stack unit comprising a plurality of electrode patterns respectively disposed for a unit device region and common electrode patterns formed to be connected to cross the unit device regions;
a second stack unit disposed on a top portion of the first stack unit and comprising a plurality of first conductor patterns;
and
a third stack unit disposed on a bottom portion of the first stack unit and comprising a plurality of second conductor patterns,
wherein the first and second conductor patterns are formed on a plurality of sheets, the first and second conductor patterns formed on one sheet are formed across a plurality of unit device regions, and the first and second conductor patterns are connected vertically through vias formed penetrating through at least some of the sheets, and
wherein the vias comprise first central vias formed on central portions of the first conductor patterns and second central vias formed on central portions of the second conductor patterns, and central axes of the first and second central vias are separated from each other.

3 more elements

A stacked chip device comprising:

a first stack unit comprising a plurality of electrode patterns respectively disposed for a unit device region and common electrode patterns formed to be connected to cross the unit device regions;
second and third stack units configured to be disposed on each of a top portion and a bottom portion of the first stack unit, each comprising a plurality of first and second conductor patterns;
and
a first via through which the first conductor pattern is vertically connected and a second via through which the second conductor pattern is vertically connected,
wherein the first via comprises a first central via and a first end portion via being formed at a central portion and an end portion of the first conductor pattern, respectively,
wherein the second via comprises a second central via and a second end portion via being formed at a central portion and an end portion of the second conductor pattern, respectively, and
wherein the first end portion via and the second end portion via are disposed at different positions and are horizontally spaced apart from each other.

4 more elements

Dependencies are inferred from the claim text.