Apparatus and methods for digital predistortion
AssigneeAltera Corporation
InventorLei Xu
Life of this patent
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Abstract
The present disclosure provides advantageously flexible and effective methods, circuits and systems for digital predistortion. In one embodiment, a predistortion component circuit includes multiple configurable delay line pairs and corresponding configurable look-up tables. Each configurable delay line pair includes a first delay line for delaying an input data signal to provide a delayed input and a second delay line for delaying an input magnitude signal to provide a delayed input magnitude. Each configurable look-up table receives the delayed input magnitude from, and outputs a look-up value for, an associated delay line pair of the plurality of configurable delay line pairs. Other embodiments, aspects and features are also disclosed herein.
Claims12
A predistortion component circuit comprising:
- a plurality of configurable delay line pairs, wherein each said configurable delay line pair includes a first delay line for delaying an input data signal to provide a delayed input and a second delay line for delaying an input magnitude signal to provide a delayed input magnitude;
- a plurality of configurable look-up tables, wherein each said configurable look-up table receives the delayed input magnitude from, and outputs a look-up value for, an associated delay line pair of the plurality of configurable delay line pairs, and wherein each said configurable look-up table is configured with computed values that depend on a memory depth and a non-linearity order;
- and
- an address generator for receiving the input data signal and generating the input magnitude signal therefrom,
- wherein the second delay line in each said configurable delay line pair receives the input magnitude signal directly from the address generator.
A method for configuring a predistortion component in a digital predistortion system, the method comprising:
- pre-determining a memory depth and a non-linearity order;
- electronically programming a plurality of delay line pairs, wherein each said delay line pair includes a first delay line for delaying an input data signal so as to provide a delayed input and a second delay line for delaying an input magnitude signal so as to provide a delayed input magnitude;
- electronically programming a plurality of look-up tables associated with said plurality of delay line pairs, wherein each said look-up table is configured with computed values that depend on the memory depth and the non-linearity order;
- generating the input magnitude signal from the input data signal using an address generator;
- and
- receiving the input magnitude signal by the second delay line in each said delay line pair directly from the address generator.
A system for digital predistortion, the system comprising:
- a predistortion component circuit for receiving an input data signal and outputting a predistorted input data signal;
- first conversion circuitry for converting the predistorted input data signal to a predistorted analog signal;
- an amplifier for amplifying the predistorted analog signal and outputting an amplified signal;
- a sampling component circuit for sampling the amplified signal to obtain a sampled analog signal;
- second conversion circuitry for converting the sampled analog signal to at least one data sample;
- and
- an adaption component circuit for receiving the at least one data sample and generating coefficients for use by the predistortion component circuit,
- wherein the predistortion component circuit includes an address generator, a plurality of configurable delay line pairs and a plurality of configurable look-up tables,
- wherein each said configurable delay line pair includes a first delay line for delaying an input data signal to provide a delayed input and a second delay line for delaying an input magnitude signal to provide a delayed input magnitude,
- wherein the address generator receives the input data signal and generates the input magnitude signal therefrom, and
- wherein the second delay line in each said configurable delay line pair receives the input magnitude signal directly from the address generator.
Dependencies are inferred from the claim text.