US 9,431,892 B1Granted

High voltage start-up circuit with adjustable start-up time

AssigneeSuzhou Poweron IC Design Co., Ltd

InventorsHaisong Li, Changshen Zhao, Ping Tao, Yangbo Yi

Life of this patent

Estimating the term…

Loading patent…

Abstract

A high voltage start-up circuit with adjustable start-up time, wherein, the drain electrode of the first NMOS transistor is connected with a first terminal of the first resistor, a gate electrode of the second NMOS transistor and a negative terminal of the diode; a source electrode of the first NMOS transistor, together with a positive terminal of the diode, is connected to the power ground; a drain electrode of the second NMOS transistor, together with a second terminal of the first resistor, is connected with a port SW of a chip; a source electrode of the second NMOS transistor, together with a first terminal of the second resistor, is connected with a power port VDD of the chip. The circuit can adjust the start-up time and the restart time of the chip flexibly.

Claims20

Dependent claims

A high voltage start-up circuit with adjustable start-up time, comprising:

a drain electrode of a first NMOS transistor connected with a first terminal of a first resistor, a gate electrode of a second NMOS transistor, and a negative terminal of a diode;
a source electrode of the first NMOS transistor, together with a positive terminal of the diode, connected to a power ground;
a drain electrode of the second NMOS transistor, together with a second terminal of the first resistor, connected with a port SW of a chip;
a source electrode of the second NMOS transistor, together with a first terminal of a second resistor, connected with a power port VDD of the chip, the power port VDD operable to generate a VDD voltage;
a second terminal of the second resistor connected with a first terminal of a third resistor and a first input end of a first comparator;
a second terminal of the third resistor connected to a power ground;
an output end of the first comparator connected with an input end of a first counter;
and
a first output end and a second output end of the first counter respectively configured to be connected with a PWM controller,
wherein
the first comparator is configured to detect a voltage level of the power port VDD of the chip and to generate a control signal Ctrl1, and
the first counter is configured to count a number of rising edges or falling edges of the control signal Ctrl1, and to generate a first initial start-up enable signal to regulate power-on start-up time of the chip and a first restart enable signal to regulate restart time of the chip.

9 more elements

A high voltage start-up circuit with adjustable start-up time, comprising:

a drain electrode of a first NMOS transistor connected with a first terminal of a first resistor, a gate electrode of a second NMOS transistor, and a negative terminal of a diode;
a source electrode of the first NMOS transistor, together with a positive terminal of the diode, connected to a power ground;
a drain electrode of the second NMOS transistor, together with a second terminal of the first resistor, connected with a port SW of a chip;
a source electrode of the second NMOS transistor, together with a first terminal of a second resistor, connected with a power port VDD of the chip, the power port VDD operable to generate a VDD voltage;
a second terminal of the second resistor connected with a first terminal of a third resistor and a first input end of a first comparator;
a second terminal of the third resistor connected to a power ground;
an output end of the first comparator connected with an input end of a first counter;
a first output end and a second output end of the first counter respectively configured to be connected with a PWM controller;
a first input end of a second comparator connected with the second terminal of the second resistor;
an output end of the second comparator connected with a second input end of a one-of-two data selector and an input end of a second counter;
a first output end and a second output end of the second counter respectively configured to be connected with the PWM controller;
a first input end of the one-of-two data selector connected with the output end of the first comparator;
a selection terminal of the one-of-two data selector connected with an output end of an OR gate;
and
a first input end and a second input end of the OR gate respectively connected with the first output end and the second output end of the first counter,
wherein
the first comparator is configured to detect a voltage level of the power port VDD of the chip and to generate a control signal Ctrl1,
the first counter is configured to count a number of rising edges or falling edges of the control signal Ctrl1, and to generate a first initial start-up enable signal to regulate power-on start-up time of the chip and a first restart enable signal to regulate restart time of the chip,
the second comparator is configured to detect the voltage level of the power port VDD and generate a control signal Ctrl2,
the control signal Ctrl2 is an internal power signal or an indication signal of the internal power, and
the second counter is configured to count the number of rising edges or falling edges of the control signal Ctrl2 and to generate a second initial start-up enable signal and a second restart enable signal.

18 more elements

A high voltage start-up circuit with adjustable start-up time, comprising:

a drain electrode of a first NMOS transistor connected with a first terminal of a first resistor, a gate electrode of a second NMOS transistor, and a negative terminal of a diode;
a source electrode of the first NMOS transistor, together with a positive terminal of the diode, connected to a power ground;
a drain electrode of the second NMOS transistor, together with a second terminal of the first resistor, connected with a port SW of a chip;
a source electrode of the second NMOS transistor, together with a first terminal of a second resistor, connected with a power port VDD of the chip, the power port VDD operable to generate a VDD voltage;
a second terminal of the second resistor connected with a first terminal of a third resistor and a first input end of a first comparator;
a second terminal of the third resistor connected to a power ground;
an output end of the first comparator connected with an input end of a first counter;
a first output end and a second output end of the first counter respectively configured to be connected with a PWM controller;
a first input end of a second comparator connected with the second terminal of the second resistor;
an output end of a one-of-two data selector is connected with a gate electrode of the first NMOS transistor;
an output end of the second comparator connected with a second input end of the one-of-two data selector and an input end of a second counter;
a first output end and a second output end of the second counter respectively configured to be connected with the PWM controller;
a first input end of the one-of-two data selector connected with the output end of the first comparator;
a selection terminal of the one-of-two data selector connected with an output end of an OR gate;
and
a first input end and a second input end of the OR gate respectively connected with the first output end and the second output end of the first counter,
wherein
the first comparator is configured to detect a voltage level of the power port VDD of the chip and to generate a control signal Ctrl1, wherein the control signal Ctrl1 controls the high voltage start-up circuit to work or stop working, thus causing a rise or a fall of the VDD voltage, thereby generating an inversion of the control signal Ctrl1, wherein the type and the number of the edges of the control signal Ctrl1, which are counted by the first counter, are configurable,
the first counter is configured to count a number of rising edges or falling edges of the control signal Ctrl1, and to generate a first initial start-up enable signal to regulate power-on start-up time of the chip and a first restart enable signal to regulate restart time of the chip,
the second comparator is configured to detect the voltage level of the power port VDD and generate a control signal Ctrl2,
the control signal Ctrl2 is an internal power signal or an indication signal of the internal power,
the second counter is configured to count the number of rising edges or falling edges of the control signal Ctrl2 and to generate a second initial start-up enable signal and a second restart enable signal,
a second input end of the first comparator is controlled by an output signal from the output end of the first comparator, and the second input end is configured to select either an input of a threshold value K×VTH1 or an input of a threshold value K×VTH2, wherein the input of the threshold value K×VTH1 and the input of a threshold value K×VTH2 are generated by the chip, and wherein the threshold value VTH2 is greater than a threshold value of the VDD voltage set for an internal power down event of the chip,
ratio K is the voltage division ratio for the VDD voltage, which depends on a circuit structure constructed by the second resistor and the third resistor, wherein
K
=
R
3
R
2
+
R
3
,
VTH1 is a threshold value of the VDD voltage when the control signal Ctrl1 inverts to a high level, VTH2 is a threshold value of the VDD voltage when the control signal Ctrl1 inverts to a low level, wherein VTH1 is greater than VTH2,
when the output signal of the first comparator is a high level, the second input end thereof selects the input of the threshold value K×VTH2,
when the output signal of the first comparator is a low level, the second input end thereof selects the input of the threshold value K×VTH1,
for the power-on start-up, the type and number of the edges of the control signal Ctrl1 are configured to be a falling edge and N1, wherein N1 can be any positive integer, and wherein for the restart, the type and number of the edges of the control signal Ctrl1 are configured to be a falling edge and N2, wherein N2 can be any positive integer,
a second input end of the second comparator is controlled by an output signal from the output end of the second comparator and the second input end is configured to select either an input of a threshold value K×VTH3 or an input of a threshold value K×VTH4, wherein the input of the threshold value K×VTH3 and the input of a threshold value K×VTH4 are generated by the chip,
ratio K is the voltage division ratio for the voltage VDD, which depends on a circuit structure constructed by the second resistor and the third resistor, wherein
K
=
R
3
R
2
+
R
3
,
VTH3 is a threshold value of the voltage VDD when the control signal Ctrl2 inverts to a high level, namely, a threshold value of the voltage VDD when an internal power is set up,
VTH4 is a threshold value of the voltage VDD when the control signal Ctrl2 inverts to a low level, namely, a threshold value of the voltage VDD when the internal power powers down, wherein, VTH3 is greater than VTH4, and VTH1 is greater than VTH2, and VTH2 is greater than VTH4,
when the output signal of the second comparator is a high level, the second input end of the second comparator selects the input of the threshold value K×VTH4,
when the output signal of the second comparator is a low level, the second input end of the second comparator selects the input of the threshold value K×VTH3,
the second comparator is configured to detect the voltage level of the power port VDD and generate a control signal Ctrl2,
the first comparator is configured to detect the voltage level of the power port VDD and generate the control signal Ctrl1,
the control signal Ctrl2 and the control signal Ctrl1 are selected to control the high voltage start-up circuit to work or stop working, thus causing a rise or a fall of the voltage VDD, thereby generating an inversion of the control signal Ctrl1 or the control signal Ctrl2,
during a power-on start-up stage, if the first initial enable signal is inactive, the control signal Ctrl1 controls the high voltage start-up circuit to work or not work,
if the first initial enable signal is active, the control signal Ctrl2 controls the high voltage start-up circuit to work or not work,
during a restart stage, if the first restart enable signal is inactive, the control signal Ctrl1 controls the high voltage start-up circuit to work or not work,
if the first restart enable signal is active, the control signal Ctrl2 controls the high voltage start-up circuit to work or not work,
the type and the number of the edges of the control signal Ctrl2, which are counted by the second counter, are configurable,
for the power-on start-up, the number of the falling edges of the control signal Ctrl2 is configured to be N3, wherein N3 can be any positive integer, and
when the chip restarts after an abnormal event, the number of the falling edges of the control signal Ctrl2 is configured to be N4, wherein N4 can be any positive integer.

61 more elements

Dependencies are inferred from the claim text.